Patents by Inventor Gi-young Yang
Gi-young Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11973081Abstract: An integrated circuit includes a first standard cell including a first first-type transistor, a first second-type transistor, a third second-type transistor, and a third first-type transistor, a second standard cell including a second first-type transistor, a second second-type transistor, a fourth second-type transistor and a fourth first-type transistor, a plurality of wiring layers which are disposed on the first and second standard cells and includes a first wiring layer, a second wiring layer, and a third wiring layer sequentially stacked. A source contact of the first first-type transistor and a source contact of the second first-type transistor are electrically connected through a first power rail of the plurality of wiring layers, and a source contact of the third first-type transistor and a source contact of the fourth first-type transistor are electrically connected through a second power rail of the plurality of wiring layers.Type: GrantFiled: December 24, 2021Date of Patent: April 30, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyeon Gyu You, In Gyum Kim, Gi Young Yang, Ji Su Yu, Jin Young Lim, Hak Chul Jung
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Publication number: 20230343788Abstract: An integrated circuit including a first active region and a second active region extending in a first direction and spaced apart from each other in a second direction intersecting the first direction; a power rail and a ground rail extending in the first direction and spaced apart from the first and second active regions and each other in the second direction; source/drain contacts extending in the second direction on at least a portion of the first or second active region, gate structures extending in the second direction and on at least a portion of the first and second active regions, a power rail configured to supply power through source/drain contact vias, and a ground rail configured to supply a ground voltage through source/drain contact vias.Type: ApplicationFiled: June 29, 2023Publication date: October 26, 2023Inventors: Gi Young Yang, Hyeon Gyu You, Ga Room Kim, Jin Young Lim, In Gyum Kim, Hak Chul Jung
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Patent number: 11735592Abstract: An integrated circuit including a first active region and a second active region extending in a first direction and spaced apart from each other in a second direction intersecting the first direction; a power rail and a ground rail extending in the first direction and spaced apart from the first and second active regions and each other in the second direction; source/drain contacts extending in the second direction on at least a portion of the first or second active region, gate structures extending in the second direction and on at least a portion of the first and second active regions, a power rail configured to supply power through source/drain contact vias, and a ground rail configured to supply a ground voltage through source/drain contact vias.Type: GrantFiled: September 23, 2020Date of Patent: August 22, 2023Inventors: Gi Young Yang, Hyeon Gyu You, Ga Room Kim, Jin Young Lim, In Gyum Kim, Hak Chul Jung
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Publication number: 20220115406Abstract: An integrated circuit includes a first standard cell including a first first-type transistor, a first second-type transistor, a third second-type transistor, and a third first-type transistor, a second standard cell including a second first-type transistor, a second second-type transistor, a fourth second-type transistor and a fourth first-type transistor, a plurality of wiring layers which are disposed on the first and second standard cells and includes a first wiring layer, a second wiring layer, and a third wiring layer sequentially stacked. A source contact of the first first-type transistor and a source contact of the second first-type transistor are electrically connected through a first power rail of the plurality of wiring layers, and a source contact of the third first-type transistor and a source contact of the fourth first-type transistor are electrically connected through a second power rail of the plurality of wiring layers.Type: ApplicationFiled: December 24, 2021Publication date: April 14, 2022Inventors: Hyeon Gyu YOU, In Gyum KIM, Gi Young YANG, Ji Su YU, Jin Young LIM, Hak Chul JUNG
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Patent number: 11244961Abstract: An integrated circuit includes a first standard cell including a first first-type transistor, a first second-type transistor, a third second-type transistor, and a third first-type transistor, a second standard cell including a second first-type transistor, a second second-type transistor, a fourth second-type transistor and a fourth first-type transistor, a plurality of wiring layers which are disposed on the first and second standard cells and includes a first wiring layer, a second wiring layer, and a third wiring layer sequentially stacked. A source contact of the first first-type transistor and a source contact of the second first-type transistor are electrically connected through a first power rail of the plurality of wiring layers, and a source contact of the third first-type transistor and a source contact of the fourth first-type transistor are electrically connected through a second power rail of the plurality of wiring layers.Type: GrantFiled: May 30, 2020Date of Patent: February 8, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyeon Gyu You, In Gyum Kim, Gi Young Yang, Ji Su Yu, Jin Young Lim, Hak Chul Jung
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Patent number: 11239151Abstract: A standard cell of an IC includes a cell area including a transistor configured to determine a function of the standard cell; a first dummy area and a second dummy area respectively adjacent to two sides of the cell area in a first direction; and an active area extending in the first direction across the cell area, the first dummy area, and the second dummy area. The active area includes a first active area and a second active area spaced apart from each other in a second direction perpendicular to the first direction and extend parallel to each other in the first direction. At least one of the first active area and the second active area provided in the first dummy area is biased, and at least one of the first active area and the second active area provided in the second dummy area is biased.Type: GrantFiled: May 28, 2020Date of Patent: February 1, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: In-gyum Kim, Ha-young Kim, Tae-joong Song, Jong-hoon Jung, Gi-young Yang, Jin-young Lim
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Publication number: 20210193683Abstract: An integrated circuit including a first active region and a second active region extending in a first direction and spaced apart from each other in a second direction intersecting the first direction; a power rail and a ground rail extending in the first direction and spaced apart from the first and second active regions and each other in the second direction; source/drain contacts extending in the second direction on at least a portion of the first or second active region, gate structures extending in the second direction and on at least a portion of the first and second active regions, a power rail configured to supply power through source/drain contact vias, and a ground rail configured to supply a ground voltage through source/drain contact vias.Type: ApplicationFiled: September 23, 2020Publication date: June 24, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Gi Young YANG, Hyeon Gyu YOU, Ga Room KIM, Jin Young LIM, In Gyum KIM, Hak Chul JUNG
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Publication number: 20210134837Abstract: An integrated circuit includes a first standard cell including a first first-type transistor, a first second-type transistor, a third second-type transistor, and a third first-type transistor, a second standard cell including a second first-type transistor, a second second-type transistor, a fourth second-type transistor and a fourth first-type transistor, a plurality of wiring layers which are disposed on the first and second standard cells and includes a first wiring layer, a second wiring layer, and a third wiring layer sequentially stacked. A source contact of the first first-type transistor and a source contact of the second first-type transistor are electrically connected through a first power rail of the plurality of wiring layers, and a source contact of the third first-type transistor and a source contact of the fourth first-type transistor are electrically connected through a second power rail of the plurality of wiring layers.Type: ApplicationFiled: May 30, 2020Publication date: May 6, 2021Inventors: Hyeon Gyu YOU, In Gyum KIM, Gi Young YANG, Ji Su YU, Jin Young LIM, Hak Chul JUNG
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Publication number: 20200294905Abstract: A standard cell of an IC includes a cell area including a transistor configured to determine a function of the standard cell; a first dummy area and a second dummy area respectively adjacent to two sides of the cell area in a first direction; and an active area extending in the first direction across the cell area, the first dummy area, and the second dummy area. The active area includes a first active area and a second active area spaced apart from each other in a second direction perpendicular to the first direction and extend parallel to each other in the first direction. At least one of the first active area and the second active area provided in the first dummy area is biased, and at least one of the first active area and the second active area provided in the second dummy area is biased.Type: ApplicationFiled: May 28, 2020Publication date: September 17, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: In-gyum KIM, Ha-young KIM, Tae-joong SONG, Jong-hoon JUNG, Gi-young YANG, Jin-young LIM
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Patent number: 10672702Abstract: A standard cell of an IC includes a cell area including a transistor configured to determine a function of the standard cell; a first dummy area and a second dummy area respectively adjacent to two sides of the cell area in a first direction; and an active area extending in the first direction across the cell area, the first dummy area, and the second dummy area. The active area includes a first active area and a second active area spaced apart from each other in a second direction perpendicular to the first direction and extend parallel to each other in the first direction. At least one of the first active area and the second active area provided in the first dummy area is biased, and at least one of the first active area and the second active area provided in the second dummy area is biased.Type: GrantFiled: June 6, 2019Date of Patent: June 2, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: In-gyum Kim, Ha-young Kim, Tae-joong Song, Jong-hoon Jung, Gi-young Yang, Jin-young Lim
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Publication number: 20190287891Abstract: A standard cell of an IC includes a cell area including a transistor configured to determine a function of the standard cell; a first dummy area and a second dummy area respectively adjacent to two sides of the cell area in a first direction; and an active area extending in the first direction across the cell area, the first dummy area, and the second dummy area. The active area includes a first active area and a second active area spaced apart from each other in a second direction perpendicular to the first direction and extend parallel to each other in the first direction. At least one of the first active area and the second active area provided in the first dummy area is biased, and at least one of the first active area and the second active area provided in the second dummy area is biased.Type: ApplicationFiled: June 6, 2019Publication date: September 19, 2019Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: In-gyum KIM, Ha-young KIM, Tae-joong SONG, Jong-hoon JUNG, Gi-young YANG, Jin-young LIM
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Patent number: 10371389Abstract: A cooking device is provided, which includes a cooking portion, a hood portion arranged on the cooking portion and provided with a suction port formed on one side thereof, and a driving portion configured to move the hood portion, wherein the hood portion is movable to any one of a first position in which the hood portion is accommodated in the cooking portion and a second position in which the hood portion projects from the cooking portion, and an angle of the hood portion is varied so as to change a direction in which the suction port is directed in the second position.Type: GrantFiled: June 17, 2016Date of Patent: August 6, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Gi-young Yang, Si-ho Jang
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Patent number: 10354947Abstract: An integrated circuit (IC) may include a plurality of standard cells. At least one standard cell of the plurality of standard cells may include a power rail configured to supply power to the at least one standard cell, the power rail extending in a first direction, a cell area including at least one transistor configured to determine a function of the at least one standard cell, a first dummy area and a second dummy area respectively adjacent to two sides of the cell area in the first direction, and an active area extending in the first direction across the cell area, the first dummy area, and the second dummy area. A region of the active area, which is included in the first dummy area or the second dummy area, is electrically connected to the power rail.Type: GrantFiled: January 15, 2018Date of Patent: July 16, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: In-gyum Kim, Ha-young Kim, Tae-joong Song, Jong-hoon Jung, Gi-young Yang, Jin-young Lim
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Patent number: 10108772Abstract: Methods of generating an integrated circuit layout include forming a standard cell by providing a first active area adjacent to a first cell boundary line. The first active area is spaced apart from the first cell boundary line by a first distance. A second active area is provided adjacent to a second cell boundary line. The second cell boundary line opposes the first cell boundary line. The second active area is spaced apart from the second cell boundary line by a second distance. Fins are formed on the first and second active areas. The fins extend in a first direction and parallel to one another in a second direction substantially perpendicular to the first direction. The first cell boundary line is parallel to the fins. The first distance and the second distance remain constant when a number of the fins on the first and second active areas is changed.Type: GrantFiled: September 21, 2016Date of Patent: October 23, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-hoon Baek, Jae-woo Seo, Gi-young Yang, Dal-hee Lee, Sung-wee Cho
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Publication number: 20180226336Abstract: An integrated circuit (IC) may include a plurality of standard cells. At least one standard cell of the plurality of standard cells may include a power rail configured to supply power to the at least one standard cell, the power rail extending in a first direction, a cell area including at least one transistor configured to determine a function of the at least one standard cell, a first dummy area and a second dummy area respectively adjacent to two sides of the cell area in the first direction, and an active area extending in the first direction across the cell area, the first dummy area, and the second dummy area. A region of the active area, which is included in the first dummy area or the second dummy area, is electrically connected to the power rail.Type: ApplicationFiled: January 15, 2018Publication date: August 9, 2018Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: In-gyum KIM, Ha-young KIM, Tae-joong SONG, Jong-hoon JUNG, Gi-young YANG, Jin-young LIM
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Patent number: 9852252Abstract: A standard cell library and a method of using the same may include information regarding a plurality of standard cells stored on a non-transitory computer-readable storage medium, wherein at least one of the plurality of standard cells includes a pin through which an input signal or an output signal of the at least one standard cell passes and including first and second regions perpendicular to a stack direction. When the via is disposed in the pin, the second region can provide a resistance value of the via smaller than that of the first region. The standard cell library may further include marker information corresponding to the second region.Type: GrantFiled: July 16, 2015Date of Patent: December 26, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-hoon Baek, Tae-joong Song, Jae-ho Park, Gi-young Yang, Jin-tae Kim, Hyo-sig Won
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Patent number: 9842182Abstract: A method of designing a semiconductor device and system for designing a semiconductor device are provided. The method of designing a semiconductor device includes providing a standard cell layout which includes an active region and a dummy region; determining a first fin pitch between a first active fin and a second active fin in the active region and a second fin pitch between a first dummy fin and a second dummy fin in the dummy region; placing the first and second active fins in the active region and the first and second dummy fins in the dummy region using the first and second fin pitches; and verifying the standard cell layout.Type: GrantFiled: September 4, 2015Date of Patent: December 12, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Hoon Baek, Tae-Joong Song, Gi-Young Yang, Jeong-Ho Do
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Patent number: 9576953Abstract: A layout design system for designing a semiconductor device includes a processor, a storage module storing an intermediate design, and a correction module used by the processor to correct the intermediate design. The intermediate design includes an active region and dummy designs on the active region. Each dummy design includes a dummy structure and dummy spacers disposed at opposite sides of the dummy structure. The correction module is configured to alter widths of regions of at least some of the dummy designs. The corrected design is used to produce a semiconductor device having an active fin, a hard mask layer disposed on the active fin, a gate structure crossing the over the hard mask layer, and a spacer disposed on at least one side of the gate structure. The hard mask layer, and the active fin, are provided with widths that vary due to the dummy designs.Type: GrantFiled: September 17, 2014Date of Patent: February 21, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Kang-Hyun Baek, Jin-Hyun Noh, Tae-Joong Song, Gi-Young Yang, Sang-Kyu Oh
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Publication number: 20170016630Abstract: A cooking device is provided, which includes a cooking portion, a hood portion arranged on the cooking portion and provided with a suction port formed on one side thereof, and a driving portion configured to move the hood portion, wherein the hood portion is movable to any one of a first position in which the hood portion is accommodated in the cooking portion and a second position in which the hood portion projects from the cooking portion, and an angle of the hood portion is varied so as to change a direction in which the suction port is directed in the second position.Type: ApplicationFiled: June 17, 2016Publication date: January 19, 2017Inventors: Gi-young Yang, Si-ho Jang
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Publication number: 20170011160Abstract: Methods of generating an integrated circuit layout include forming a standard cell by providing a first active area adjacent to a first cell boundary line. The first active area is spaced apart from the first cell boundary line by a first distance. A second active area is provided adjacent to a second cell boundary line. The second cell boundary line opposes the first cell boundary line. The second active area is spaced apart from the second cell boundary line by a second distance. Fins are formed on the first and second active areas. The fins extend in a first direction and parallel to one another in a second direction substantially perpendicular to the first direction. The first cell boundary line is parallel to the fins. The first distance and the second distance remain constant when a number of the fins on the first and second active areas is changed.Type: ApplicationFiled: September 21, 2016Publication date: January 12, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Sang-hoon BAEK, Jae-woo SEO, Gi-young YANG, Dal-hee LEE, Sung-wee CHO