Abstract: A matrix switch system is described with which a large number of communication lines can be interconnected. The lines are arranged in multiplex groups which are in turn sampled by multiplexers. The multiplexers in turn are coupled to matrix lines which intersect at connectable crosspoints. A common timing signal with a predetermined minimum number of time slices is used to reconfigure the system during each time slice and form the desired line connections through the multiplexers and crosspoints for signal transfer. A technique is described to allocate time slices for the various connections of the lines and minimize matrix lock conditions.

Abstract: A switch matrix system is described with which peripheral devices can be conveniently tested for compatibility with central processor units. A diagnostic channel is provided to which a peripheral device to be tested is connected at a crosspoint in the switch matrix system. A control provides a sequence of signals needed to establish data communication between the central processor unit and the peripheral device. Errors or failures in the sequence are detected and stored and displayed with a terminal from which the switch matrix system is operated. Additional testing is done by generating bit test patterns and comparing the returns with those sent out. A channel activity monitor is employed in the switch matrix system to enable a comparative review of activity of channels from different central processor units.

Abstract: Various data systems as represented by several processing units have permanent multiple switch connections to a common set of peripheral devices. A coordinating actuator means is provided for each set of switches connecting together a peripheral device and a CPU so that the coordinating actuator means for all possible combinations may be conceived as being arranged in a matrix consisting of columns and rows, along one axis of which are arranged the CPU's and along the other axis of which are arranged the peripheral devices. The present invention provides a panel means having indicator elements arranged in a matrix pattern of columns and rows to simulate the switching matrix so that each column repesents a particular device of one kind, CPU or peripheral device, and each row represents a particular device of the other kind.