Abstract: A test circuit aids in accurately measuring the input pin to output pin signal propagation speed through an integrated circuit by providing a D flip-flop in the signal path near the output pad to register the arrival of a test signal transition. The flip-flop is clocked at various clock frequencies. At the high frequencies, test signal transitions applied at the input pad coincident with a clock transition having not arrived at the output pad in time to be registered at the next clock transition. At lower clock frequencies, the test transition has time to propagate through the integrated circuit and thus will be registered by the flip-flop. By successively lowering the clock frequency and sending test signals through the circuit, one-half of that clock period that just registers the test signal transition corresponds to the input-to-output delay time being measured.