Abstract: One-time programmable (OTP) nonvolatile fuse memory cells are disclosed that do not require decoding or addressing for reading their data content. Each fuse memory cell has its content latched at its output and available at all times and can be used, for example, for code storage memories, serial configuration memories, and as individual fuse bits for ID (identification), trimming, and other post-fabrication System-on-Chip (SoC) customization needs. Means are also provided for temporary data storage for design testing, etc. In alternative embodiments, using two differentially programmed fuses in a single memory cell, the selection and programming circuitry are merged.

Abstract: One-time programmable (OTP) nonvolatile fuse memory cells are disclosed that do not require decoding or addressing for reading their data content. Each fuse memory cell has its content latched at its output and available at all times and can be used, for example, for code storage memories, serial configuration memories, and as individual fuse bits for ID (identification), trimming, and other post-fabrication System-on-Chip (SoC) customization needs.

Abstract: A programmable memory cell formed useful in a memory array having column bitlines and row wordlines. The memory cell including a breakdown transistor having its gate connected to a program wordline and a write transistor connected in series at a sense node to said breakdown transistor. The gate of the write transistor is connected to a write wordline. Further, a first sense transistor has its gate connected to the sense node. A second sense transistor is connected in series to the first sense transistor and has its gate connected to a read wordline. The second sense transistor has its source connected to a column bitline.

Abstract: Control circuitry for applying voltages to a memory circuit. In accordance with this invention, row circuitry applies either a high voltage or a low voltage to a memory cell based on the operation to be performed and column circuitry applies a high or a low voltage to the memory cell based on the operation to be performed.

Abstract: Control circuitry for applying voltages to a memory circuit. In accordance with this invention, row circuitry applies either a high voltage or a low voltage to a memory cell based on the operation to be performed and column circuitry applies a high or a low voltage to the memory cell based on the operation to be performed.

Abstract: Control circuitry for applying voltages to a memory circuit. In accordance with this invention, row Row circuitry applies either a high voltage or a low voltage to a memory cell based on the operation to be performed and column circuitry applies a high or a low voltage to the memory cell based on the operation to be performed.