Abstract: A method for implementing scheduling mechanisms with selectable resource modes comprises at least one resource characterization set that includes a plurality of resource characterizations that each have resource requirements for executing a requested process. The plurality of resource characterizations may include a most mode, a best mode, and a worst mode. An allocation manager may then select a resource mode, and compare the corresponding resource requirements for the requested process to the currently-available device resources. The allocation manager may then authorize or deny the requested process depending upon whether the currently-available resources are sufficient to adequately service the resource requirements of the requested process.

Abstract: A system for providing deterministic performance from a non-deterministic device comprises one or more nodes that perform isochronous and/or non-isochronous data transfer operations onto an input/output bus of an electronic device. A bandwidth manager preferably programs a deterministic interface with a maximum data value that is selected to prevent non-isochronous conflicts for control of the input/output bus to thereby permit successfully execution of deterministically-scheduled isochronous data transfers. The deterministic interface preferably may interrupt a non-isochronous data transfer operation whenever a data-unit total from transferred data equals the corresponding programmed maximum data value. An interrupted node may then attempt to complete the non-isochronous data transfer operation in subsequent isochronous cycles.

Abstract: A system and method for delivering data packets in an electronic interconnect comprises a talker device that transmits one or more data packets over a transmission path to a listener device through one or more bus bridges that each couple adjacent busses in the electronic interconnect. Each data packet includes a time stamp that indicates when the corresponding data packet is scheduled for presentation to the listener device. An initial bus bridge preferably creates a marker packet that is propagated through the transmission path to record delay information corresponding to delay elements such as the intervening bus bridges. A final bus bridge may then utilize the delay information from the marker packet to update the time stamps of the data packets to thereby incorporate the total propagation delay of the transmission path.

Abstract: A method and system for providing cyclic redundancy check (CRC) functions within a ringlet-type interconnect of a computer system are described. By time multiplexing CRC checking and generating functions, the number of CRC units can be reduced.

Abstract: A multiple function peripheral connecting device that allows more functionality in the limited port space of a computer is disclosed. The connecting device provides the capability for external devices having different functions to be connected to the computer through a single port. This is accomplished by wiring a first function, internal to the computer, to certain pins of a modular connector, and wiring a second function, also internal to the computer, to a certain different combination of pins on the same modular connector. Because differently sized plugs can fit with the modular connector, peripherals associated with different types of systems can connect with the computer through the same single jack. Also, an adapter may be connected to the computer to allow simultaneous use of the two internal functions.

Abstract: A system and method for avoiding starvation and deadlocks in a split-response-bus multiprocessor computer system. The multiprocessor computer system includes a first node and a second node coupled to the a split-response bus, wherein the first and second nodes communicate by passing request packets over the split-response bus. The method and system includes providing precedence information in the request packets, and then using the precedence information when receiving the request packets to determine which request packets to process and which request packets to reject when a conflict occurs.

Abstract: A system and method for coordinating the transmission and receipt of large data blocks as a series of smaller burst transfers through an intermediate interconnect coupling a pair of devices. A device receiving a transaction request ("initiator") specifies the data block size of the requested transaction to the other device ("target"). The target response will indicate that it is committed to the transaction, that it does not support requested transactions of the specified data block size, or that it currently lacks the buffer capacity to commit to the requested transaction. In the first instance, the initiator and target exchange the data block through the interconnect as a series of burst transfers until all data has been transferred, at which time the initiator (for read transactions) or the target (for write transactions) forwards the transferred data as a data block of the specified size.

Abstract: A system and method for avoiding starvation and deadlocks in a split-response-bus multiprocessor computer system. The multiprocessor computer system includes a first node and a second node coupled to the a split-response bus, wherein the first and second nodes communicate by passing request packets over the split-response bus. The method and system includes providing precedence information in the request packets, and then using the precedence information when receiving the request packets to determine which request packets to process and which request packets to reject when a conflict occurs.

Abstract: A system for controlling memory accesses in a memory device in a multi-processor computer system comprises a memory controller and a data storage. The data storage comprises a plurality of memory lines. Each memory line has a check field for storing a GONE code that indicates that the data is held in a cache, a g bit field for storing a G bit for confirming the code in the check field, a tag field for storing an identification of the processor in whose cache the data is held, and a d bit field for storing the true value of the G bit in rare situations. The memory controller comprises a data buffer, an address buffer, and a memory sequencer. The memory sequencer is a state machine for controlling the functions of the memory device.

Abstract: A system and method for multicasting control signals to selectively operate one memory device or groups of memory devices comprises a memory controller coupled to a plurality of memory devices by a command bus and a data bus. Each of the plurality of memory devices has a unique identification number. The system provides an addressing scheme in which an individual memory device or groups of memory device can be selected for operation by addressing the devices with a command packet. The memory controller broadcasts a command packet over the command bus to the plurality of memory devices. The packet includes an identification number. At each of the memory devices, selection logic is included to make the memory device operational if the identification number in the packet matches the identification number assigned to the memory device.

Abstract: A system for efficiently supporting critical-word-first data transfers comprises a data storage device, a controller, a data selector, and a multiplexer. The data storage device is preferably capable of outputting data in one or more word orderings. The controller is preferably a state machine that processes data transfer requests by determining the orderings of data that the associated data storage device, data selector and multiplexer can provide, determining the ordering for the data requested and creating a response packet with the data ordered in critical-word-aligned order beginning with the word containing the requested address. The present invention also includes a method for efficiently supporting critical-word-first data transfers.

Abstract: A method and system for efficiently routing data packets in a computer interconnect includes a plurality of nodes forming a ringlet, generally including two connections between each pair of nodes configured to allow communication in either direction between each pair of nodes. One sequence of such connections forms a run moving,-for example left-to-right between a series of nodes. The other sequence of connections forms a right-to-left run. Selected nodes are configured to provide two cross-over paths, each from one run to the other, so the two runs are linked to form a circle or ringlet. One or more selected nodes provide an optional connection between the two runs, thus allowing a fast path or short cut to the opposing run. A fast path may include a uni- or bidirectional cross through path in an intermediate node.

Abstract: An apparatus for performing indivisible memory operations on memory locations in remote memory means in multiple bus, multiple processor computer systems comprises a logic supervisor coupled to a bus bridge. The logic supervisor comprises a lock address register, a buffer address register, a command register, a first parameter register, a second parameter register, a first latch, a second latch, a comparator, and a controller. The controller is a state machine that observes instruction sequences intended to create an indivisible memory operation on a remote bus. When the logic supervisor detects an indivisible memory operation instruction sequence with a remote address, it gathers the data for the indivisible memory operation, inhibits the processor, and hands the data off to the bus bridge. When the logic supervisor receives a completion status from the bus bridge it places the returned value in memory and releases the processor.

Abstract: A multi-processor computer system comprising a data storage device, a memory controller, and a plurality of processors. The data storage device has a plurality of memory lines, each memory line having a portion for alternatively storing data or, a set of GONE codes, a count value, and a processor identification code value. A memory controller coupled to the data storage alternatively stores and retrieves data or the GONE code, the count field value and the processor identification code value. At least one of the processors includes a cache memory and a cache memory controller. The cache memory controller compares a GONE code associated with the requested memory line with the contents of the requested memory line, and requests the contents of the requested memory line from a second of the processors in response to the comparison.

Abstract: An elasticity buffer for use in a data transmission system having a transmitter and a receiver and utilizing a data transfer protocol that periodically supplies an elasticity element that can be deleted or replicated by the elasticity buffer to maintain the synchronous transfer of data elements.