Patents by Inventor Glen Eugene Sater

Glen Eugene Sater has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5861882
    Abstract: Multiple testing elements (26) are coupled to a bus (25) operated under the control of a graphically programmed computer (12). The computer (12) interrogates the bus (25) to identify the testing elements (26) coupled thereto. Icons (44) representing the testing elements (26) are displayed in an "Equipment Shelf" window (40). The user drags icons (44') from this window (40) onto a "Test Bench" window (42) and draws lines between I/O ports (4531 . . . 4431) on the icons (453 . . . 443) to graphically create a test circuit (54). The computer (12) generates bus commands to activate switches (28) to couple the testing elements (26) in the same manner as the graphical test circuit (54). Graphically set test ranges and parameters (472-494) are automatically sent to the testing elements (26) and test results (470) presented on the same computer display (16). The system (10) may be dynamically reconfigured for different tests without hand rewiring or loading of other test programs.
    Type: Grant
    Filed: April 4, 1997
    Date of Patent: January 19, 1999
    Assignee: Motorola, Inc.
    Inventors: Michael Kent Sprenger, Glen Eugene Sater
  • Patent number: 5793749
    Abstract: A communication system (10) includes a duplex digital communication node (14) and a half-duplex digital communication node (12). The half-duplex node (12) is configured to perform duplex testing. The half-duplex node (12) digitizes a test message (74), vocodes the test message (76), possibly encrypts the test message (78), FEC encodes the test message (80), assembles the test message into frames (82), and records the framed test message (84). During a duplex test mode of operation, the node (12) retrieves the test message (92) and transmits (90) it away from the node (12). During the duplex test mode, the node (12) also receives a signal, disassembles signal data from frames (114), FEC decodes the data (116), possibly decrypts the data (118), de-vocodes the data (120), and converts the resulting data stream into analog data (122).
    Type: Grant
    Filed: September 15, 1995
    Date of Patent: August 11, 1998
    Assignee: Motorola, Inc.
    Inventors: Arthur Paul Helwig, Glen Eugene Sater, John Richard Rezek