Abstract: An apparatus for integrating wafer scale semiconductor integrated circuits and interfacing them with other systems. A wafer, partial wafer, die or plurality of same are mated to a printed circuit board (PCB) which electrically contacts the pads on each die using small conductive pillars. The PCB in turn is connected easily to other electronic systems. The entire apparatus is incorporated into other systems which utilize the dice in the apparatus. The apparatus may be fitted with heating elements and cooling channels to generate the necessary die temperatures for burn-in, testing, and operation. The apparatus is easily adaptable to include more dice in a stacked configuration.

Abstract: A method of forming electrically conductive pillars on a printed circuit board by providing a printed circuit board having a plurality of electrical traces and forming a plurality of elongate, electrically conductive pillars of superimposed layers of solder and conductive polymer on the printed circuit board. The elongate, electrically conductive pillars are connected by a first end to the electrical traces of the printed circuit board and extend substantially perpendicularly from the printed circuit board such that a second end of each of the plurality of elongate, electrically conductive pillars lies in substantially a common plane which is substantially perpendicular to and above said printed circuit board.

Abstract: An apparatus for wafer scale burn-in and testing of semiconductor integrated circuits and a method for its utilization is disclosed. A wafer is mated to a printed circuit board which electrically contacts the pads on each die using small conductive pillars. Single precise alignment of entire wafer within apparatus allows for testing all the dice on the wafer in parallel, eliminating need to probe each die individually. The apparatus is fitted with heating elements and cooling channels to generate the necessary wafer temperatures for burn-in and testing. The method of utilization eliminates processing of defective dice beyond burn-in and test, thereby increasing throughput.

Abstract: An apparatus for integrating wafer scale semiconductor integrated circuits and interfacing them with other systems. A wafer, partial wafer, die or plurality of same are mated to a printed circuit board (PCB) which electrically contacts the pads on each die using small conductive pillars. The PCB in turn is connected easily to other electronic systems. The entire apparatus is incorporated into other systems which utilize the dice in the apparatus. The apparatus may be fitted with heating elements and cooling channels to generate the necessary dice temperatures for burn-in, testing, and operation. The apparatus is easily adaptable to include more dice in a stacked configuration.

Abstract: An apparatus for integrating wafer scale semiconductor integrated circuits and interfacing them with other systems. A wafer, partial wafer, die or plurality of same are mated to a printed circuit board (PCB) which electrically contacts the pads on each die using small conductive pillars. The PCB in turn is connected easily to other electronic systems. The entire apparatus is incorporated into other systems which utilize the dice in the apparatus. The apparatus may be fitted with heating elements and cooling channels to generate the necessary dice temperatures for burn-in, testing, and operation. The apparatus is easily adaptable to include more dice in a stacked configuration.

Abstract: An apparatus for wafer scale burn-in and testing of semiconductor integrated circuits and a method for its utilization. A wafer is mated to a printed circuit board which electrically contacts the pads on each die using small conductive pillars. Single precise alignment of entire wafer within apparatus allows for testing all the dice on the wafer in parallel, eliminating need to probe each die individually. The apparatus is fitted with heating elements and cooling channels to generate the necessary wafer temperatures for burn-in and testing. The method of utilization eliminates processing of defective dice beyond burn-in and test, thereby increasing throughput.

Abstract: An integrated series capacitor includes two capacitors mounted in series in a unitary insulated package. The capacitors are formed of stacked plates separated by a dielectric material. Every other stacked plate for each capacitor terminates along an outer termination edge that is connected to a solder connection on an end of the insulated package. These stacked plates alternate with every other plate which has an inner termination edge. The inner termination edges of each capacitor are connected. The integrated series capacitor is adapted for connection to a circuit board between a chip supply voltage (Vss) and a ground connection (Vss) to provide a decoupling circuit to replace two separate series wired capacitors.