Abstract: An instruction sequencer for programming parallel operations of functional units in response to an instruction stream is shown. The instruction sequencer includes a random access memory for storing instruction segments which program the operations of the functional units. An instruction address register contains instruction addresses for selected locations in the memory having instruction segments stored therein. A memory address circuit reads out an instruction stream comprising instruction segments from the memory in response to the stored instruction address and stores the same in an instruction buffer register. A rotating network, which is operatively coupled to the instruction buffer register, rotates the instruction stream so as to position a selected instruction segment at a predetermined location in a rotating network.

Abstract: A bus arbitration system for use in a data processing system which operates on clocked cycles for determining priorities in accessing a system memory and one or more local memories associated with processor units is shown. Each of the processor units are operatively coupled through a local bus to its associated local memory. A system bus interconnects the processor units and local memories in parallel to the local bus and the system is connected to an input/output device and the system memory. The bus arbitration system monitors requests made by processor units or the input/output device for access to the system memory or a local memory during the clock cycle. A determination section of a bus arbitration module determines whether access is available over the system data bus or a local data bus.