Patents by Inventor Glenn C. MacDougall

Glenn C. MacDougall has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Self-aligned emitter-base region
    Patent number: 9276093
    Abstract: Aspects of the invention provide a method of forming a bipolar junction transistor. The method includes: providing a semiconductor substrate including a uniform silicon nitride layer over an emitter pedestal, and a base layer below the emitter pedestal; applying a photomask at a first end and a second end of a base region; and performing a silicon nitride etch with the photomask to simultaneously form silicon nitride spacers adjacent to the emitter pedestal and exposing the base region of the bipolar junction transistor. The silicon nitride etch may be an end-pointed etch.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: March 1, 2016
    Assignee: GlobalFoundries, Inc.
    Inventors: Margaret A. Faucher, Paula M. Fisher, Thomas H. Gabert, Joseph P. Hasselbach, Qizhi Liu, Glenn C. MacDougall
  • SELF-ALIGNED EMITTER-BASE REGION
    Publication number: 20150054123
    Abstract: Aspects of the invention provide a method of forming a bipolar junction transistor. The method includes: providing a semiconductor substrate including a uniform silicon nitride layer over an emitter pedestal, and a base layer below the emitter pedestal; applying a photomask at a first end and a second end of a base region; and performing a silicon nitride etch with the photomask to simultaneously form silicon nitride spacers adjacent to the emitter pedestal and exposing the base region of the bipolar junction transistor. The silicon nitride etch may be an end-pointed etch.
    Type: Application
    Filed: October 23, 2014
    Publication date: February 26, 2015
    Inventors: Margaret A. Faucher, Paula M. Fisher, Thomas H. Gabert, Joseph P. Hasselbach, Qizhi Liu, Glenn C. MacDougall
  • Self-aligned emitter-base region
    Patent number: 8932931
    Abstract: Aspects of the invention provide a method of forming a bipolar junction transistor. The method includes: providing a semiconductor substrate including a uniform silicon nitride layer over an emitter pedestal, and a base layer below the emitter pedestal; applying a photomask at a first end and a second end of a base region; and performing a silicon nitride etch with the photomask to simultaneously form silicon nitride spacers adjacent to the emitter pedestal and exposing the base region of the bipolar junction transistor. The silicon nitride etch may be an end-pointed etch.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: January 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Margaret A. Faucher, Paula M. Fisher, Thomas H. Gabert, Joseph P. Hasselbach, Qizhi Liu, Glenn C. MacDougall
  • SELF-ALIGNED EMITTER-BASE REGION
    Publication number: 20130207235
    Abstract: Aspects of the invention provide a method of forming a bipolar junction transistor. The method includes: providing a semiconductor substrate including a uniform silicon nitride layer over an emitter pedestal, and a base layer below the emitter pedestal; applying a photomask at a first end and a second end of a base region; and performing a silicon nitride etch with the photomask to simultaneously form silicon nitride spacers adjacent to the emitter pedestal and exposing the base region of the bipolar junction transistor. The silicon nitride etch may be an end-pointed etch.
    Type: Application
    Filed: February 13, 2012
    Publication date: August 15, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Margaret A. Faucher, Paula M. Fisher, Thomas H. Gabert, Joseph P. Hasselbach, Qizhi Liu, Glenn C. MacDougall
  • Method for fabricating doped polysilicon lines
    Patent number: 7303952
    Abstract: A method of fabricating polysilicon lines and polysilicon gates, the method of including: providing a substrate; forming a dielectric layer on a top surface of the substrate; forming a polysilicon layer on a top surface of the dielectric layer; implanting the polysilicon layer with N-dopant species, the N-dopant species about contained within the polysilicon layer; implanting the polysilicon layer with a nitrogen containing species, the nitrogen containing species essentially contained within the polysilicon layer.
    Type: Grant
    Filed: October 4, 2004
    Date of Patent: December 4, 2007
    Assignee: International Business Machines Corporation
    Inventors: James W. Adkisson, John J. Ellis-Monaghan, Glenn C. MacDougall, Dale W. Martin, Kirk D. Peterson, Bruce W. Porth
  • Method for reducing dark current effects in a charge couple device
    Patent number: 6271054
    Abstract: The dark current defects in a charge couple device are reduced by employing a hydrogen anneal followed by depositing a silicon nitride barrier layer by RTCVD.
    Type: Grant
    Filed: June 2, 2000
    Date of Patent: August 7, 2001
    Assignee: International Business Machines Corporation
    Inventors: Arne W. Ballantine, George A. Dunbar, III, James V. Hart, III, Donna K. Johnson, Glenn C. MacDougall