Abstract: An SMP computer system has an apparatus and method for recalibrating a self-timed, source-synchronous, pipelined interface while the computer system is running. The apparatus allows for quiescing the interface (ie. idling the processors to allow for no data transfers), raising fences (blocking interfaces), allowing for a quick clock centering recalibration step, and then unfencing and unquiescing to allow for the use of the interface again. The recalibration allows for compensating for drift over time on the interface to compensate for temperature, voltage, cycle time, and end-of-life degradation without bringing down and restarting the system.

Abstract: An abstraction based multi-phase method for VLSI chip floorplanning is described. The abstraction based approach provides a solution to macro floorplanning in the presence of leaf level intermediate logic, and achieves it without loss of accuracy in the results. Annotations generated during abstraction are presented as floorplanning constraints which account for the abstracted data. The floorplanning and placement algorithms handle detailed netlists consisting of large blocks and small leaf level cells in an efficient manner. The abstraction based approach phases out by abstracting the leaf level logic (thus reducing the solution space of the floorplanner) and reintroducing them in the form of floorplan constraints (to account for the presence of the leaf level logic while determining the location of large blocks). The abstraction and bundling phases achieves a significant improvement in the performance of a simulated annealing based floorplanner.

Abstract: An abstraction based multi-phase method for VLSI chip floorplanning is described. The abstraction based approach provides a solution to macro floorplanning in the presence of leaf level intermediate logic, and achieves it without loss of accuracy in the results. Annotations generated during abstraction are presented as floorplanning constraints which account for the abstracted data. The floorplanning and placement algorithms handle detailed netlists consisting of large blocks and small leaf level cells in an efficient manner. The abstraction based approach phases out by abstracting the leaf level logic (thus reducing the solution space of the floorplanner) and reintroducing them in the form of floorplan constraints (to account for the presence of the leaf level logic while determining the location of large blocks). The abstraction and bundling phases achieves a significant improvement in the performance of a simulated annealing based floorplanner.

Abstract: An exemplary embodiment of the invention is a method and apparatus for configuring system cycle time in a data processing system with at least one master latch clock generating a master latch clock signal and at least one slave latch clock generating a slave latch clock signal. Timing errors are detected during system hardware testing. Adjustments to the system timing are calculated based on error for at least one of a master latch clock signal and a slave latch clock signal. The on-cycle edge of at least one of the master latch clock signal and slave latch clock signal is adjusted based on the calculations while maintaining a corresponding mid-cycle edge of at least one of the master latch clock signal and the slave latch clock signal.

Abstract: A method, computer software, and system for performing congestion mitigation in an IC design while preserving global logic order, comprising the steps of carrying out circuit block placement; measuring the congestion for each circuit block to determine if it exceeds a target value; reallocating area to circuit blocks that exceed said target value of congestion solely from adjacent circuit blocks; and removing overlap.

Abstract: An SMP computer system has an apparatus and method for recalibrating a self-timed, source-synchronous, pipelined interface while the computer system is running. The apparatus allows for quiescing the interface (ie. idling the processors to allow for no data transfers), raising fences (blocking interfaces), allowing for a quick clock centering recalibration step, and then unfencing and unquiescing to allow for the use of the interface again. The recalibration allows for compensating for drift over time on the interface to compensate for temperature, voltage, cycle time, and end-of-life degradation without bringing down and restarting the system.

Abstract: An automated, custom personalization process for generating integrated gate array chips is defined which enhances yield and reliability potential. Unused data provided in the general purpose design is deleted through a selective detection procedure based on circuit utilization.