Abstract: An input apparatus for a logic analyzer is disclosed which receives a plurality of logic signals from a probe, the plurality of logic signals being received at different points in time, the input apparatus being capable of generating a corresponding plurality of logic signals in response thereto, the time of generation of the corresponding plurality of logic signals substantially coinciding with the time of generation of a corresponding reference logic signal. The input apparatus comprises a plurality of tapped delay lines corresponding to the plurality of received logic signals. A controller controls the amount of time delay for each delay line associated with each received logic signal. The controller continues this control function until the time of generation of the corresponding plurality of logic signals substantially coincides with the time of generation of the corresponding reference logic signal.