Patents by Inventor Glenn J. Hinton
Glenn J. Hinton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180004432Abstract: Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory. The far memory is presented as “main memory” to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.Type: ApplicationFiled: June 26, 2017Publication date: January 4, 2018Inventors: Eric J. DAHLEN, Glenn J. HINTON, Raj K. RAMANUJAN
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Publication number: 20170249250Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.Type: ApplicationFiled: March 13, 2017Publication date: August 31, 2017Inventors: Raj K. RAMANUJAN, Rajat AGARWAL, Kai CHENG, Taarinya POLEPEDDI, Camille C. RAAD, David J. ZIMMERMAN, Muthukumar P. SWAMINATHAN, Dimitrios ZIAKAS, Mohan J. KUMAR, Bassam N. COURY, Glenn J. HINTON
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Patent number: 9703562Abstract: A processor of an aspect includes decode logic to receive a first instruction and to determine that the first instruction is to be emulated. The processor also includes emulation mode aware post-decode instruction processor logic coupled with the decode logic. The emulation mode aware post-decode instruction processor logic is to process one or more control signals decoded from an instruction. The instruction is one of a set of one or more instructions used to emulate the first instruction. The one or more control signals are to be processed differently by the emulation mode aware post-decode instruction processor logic when in an emulation mode than when not in the emulation mode. Other apparatus are also disclosed as well as methods and systems.Type: GrantFiled: March 16, 2013Date of Patent: July 11, 2017Assignee: Intel CorporationInventors: William C. Rash, Bret L. Toll, Scott D. Hahn, Glenn J. Hinton
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Patent number: 9690493Abstract: Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory. The far memory is presented as “main memory” to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.Type: GrantFiled: June 22, 2015Date of Patent: June 27, 2017Assignee: Intel CorporationInventors: Eric J. Dahlen, Glenn J. Hinton, Raj K. Ramanujan
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Patent number: 9600416Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.Type: GrantFiled: September 30, 2011Date of Patent: March 21, 2017Assignee: Intel CorporationInventors: Raj K. Ramanujan, Rajat Agarwal, Kai Cheng, Taarinya Polepeddi, Camille C. Raad, David J. Zimmerman, Muthukumar P. Swaminathan, Dimitrios Ziakas, Mohan J. Kumar, Bassam N. Coury, Glenn J. Hinton
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Patent number: 9594648Abstract: In one embodiment, the present invention includes a method for controlling redundant execution such that if an exceptional event occurs, the redundant execution is stopped, non-redundant execution is performed in one of the threads until the exceptional event has been-resolved, after which a state of the threads is synchronized, and redundant execution is continued. Other embodiments are described and claimed.Type: GrantFiled: December 30, 2008Date of Patent: March 14, 2017Assignee: Intel CorporationInventors: Glenn J. Hinton, Steven E. Raasch, Sebastien Hily, John G. Holm, Ronak Singhal, Avinash Sodani, Deborah T. Marr
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Publication number: 20170031821Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.” In one embodiment, the “near memory” is configured to operate in a plurality of different modes of operation including (but not limited to) a first mode in which the near memory operates as a memory cache for the far memory and a second mode in which the near memory is allocated a first address range of a system address space with the far memory being allocated a second address range of the system address space, wherein the first range and second range represent the entire system address space.Type: ApplicationFiled: June 24, 2016Publication date: February 2, 2017Inventors: Raj K. RAMANUJAN, Rajat AGARWAL, Glenn J. HINTON
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Patent number: 9423959Abstract: An apparatus and method are described for store durability and ordering in a persistent memory architecture. For example, one embodiment of a method comprises: performing at least one store operation to one or more addresses identifying at least one persistent memory device, the store operations causing one or more memory controllers to store data in the at least one persistent memory device; sending a request message to the one or more memory controllers instructing the memory controllers to confirm that the store operations are successfully committed to the at least one persistent memory device; ensuring at the one or more memory controllers that at least all pending store operations received at the time of the request message will be committed to the persistent memory device; and sending a response message from the one or more memory controllers indicating that the store operations are successfully committed to the persistent memory device.Type: GrantFiled: June 29, 2013Date of Patent: August 23, 2016Assignee: Intel CorporationInventors: Subramanya R. Dulloor, Sanjay Kumar, Rajesh M. Sankaran, Gilbert Neiger, Richard A. Uhlig, Robert S. Chappell, Joseph Nuzman, Kai Cheng, Sailesh Kottapalli, Yen-Cheng Liu, Mohan Kumar, Raj K. Ramanujan, Glenn J. Hinton
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Patent number: 9418700Abstract: A system includes a non-volatile random access memory (NVRAM) device and controller logic that detects a bad block within the device, retires the bad block and replaces the bad block with a replacement block by assigning the address of the bad block to the replacement block.Type: GrantFiled: June 29, 2012Date of Patent: August 16, 2016Assignee: Intel CorporationInventors: Raj K. Ramanujan, Glenn J. Hinton, David J. Zimmerman
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Patent number: 9378142Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.” In one embodiment, the “near memory” is configured to operate in a plurality of different modes of operation including (but not limited to) a first mode in which the near memory operates as a memory cache for the far memory and a second mode in which the near memory is allocated a first address range of a system address space with the far memory being allocated a second address range of the system address space, wherein the first range and second range represent the entire system address space.Type: GrantFiled: September 30, 2011Date of Patent: June 28, 2016Assignee: Intel CorporationInventors: Raj K. Ramanujan, Rajat Agarwal, Glenn J. Hinton
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Publication number: 20160041772Abstract: Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory. The far memory is presented as “main memory” to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.Type: ApplicationFiled: June 22, 2015Publication date: February 11, 2016Inventors: Eric J. Dahlen, Glenn J. Hinton, Raj K. Ramanujan
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Patent number: 9146873Abstract: Examples are disclosed for establishing a window for a queue structure maintained in a cache for a processing element for a network device. The processing element may be configured to operate in cooperation with an input/output device such as a network interface card. In some of these examples, the window may include portions of the queue structure having identifiers to active allocated buffers maintained in memory for the network device. The active allocated buffers may be configured to maintain or store data received or to be forwarded by the input/output device. For these examples, the window may be adjusted based on information gathered while the identifiers are read from or written to the portions of the queue structure.Type: GrantFiled: March 30, 2012Date of Patent: September 29, 2015Assignee: INTEL CORPORATIONInventors: Anil Vasudevan, Glenn J. Hinton, Yadong Li
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Patent number: 9141461Abstract: A technology for implementing a method for a machine check architecture environment. A method of the disclosure includes obtaining an occurrence of an error. The occurrence of the error causes a non-microcoded processing device to enter an error monitoring state. The method further processes the error using a dedicated memory portion for the error monitoring state while the non-microcoded processing device is in the error monitoring state. The error monitoring state is dedicated to error processing. The method further determines information associated with the error. The information associated with the error is in a predefined format.Type: GrantFiled: June 23, 2013Date of Patent: September 22, 2015Assignee: Intel CorporationInventors: Willam C. Rash, Scott D. Hanh, Glenn J. Hinton
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Patent number: 9087584Abstract: Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory. The far memory is presented as “main memory” to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.Type: GrantFiled: December 13, 2013Date of Patent: July 21, 2015Assignee: Intel CorporationInventors: Eric J. Dahlen, Glenn J. Hinton, Raj K. Ramanujan
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Patent number: 9081688Abstract: In one embodiment, the present invention includes a method for providing a cache block in an exclusive state to a first cache and providing the same cache block in the exclusive state to a second cache when cores accessing the two caches are executing redundant threads. Other embodiments are described and claimed.Type: GrantFiled: December 30, 2008Date of Patent: July 14, 2015Assignee: Intel CorporationInventors: Glenn J. Hinton, Steven E. Raasch, Sebastien Hily, John G. Holm, Ronak Singhal, Avinash Sodani, Deborah T. Marr, Shubhendu S. Mukherjee, Arijit Biswas, Adrian C. Moga
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Publication number: 20150186140Abstract: Embodiments of an invention for opcode trapping are disclosed. In one embodiment, a processor includes an instruction unit to receive an instruction, the instruction unit having a match storage location in which to store a match value and a comparator. The comparator is to compare the match value to a portion of the instruction. Control of the processor is to be transferred to a trap handler if the comparator indicates that the match value matches the portion of the instruction.Type: ApplicationFiled: December 28, 2013Publication date: July 2, 2015Inventors: Bret L. Toll, Buford M. Guy, Ronak Singhal, Glenn J. Hinton, Mishali Naik
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Publication number: 20150006834Abstract: An apparatus and method are described for store durability and ordering in a persistent memory architecture. For example, one embodiment of a method comprises: performing at least one store operation to one or more addresses identifying at least one persistent memory device, the store operations causing one or more memory controllers to store data in the at least one persistent memory device; sending a request message to the one or more memory controllers instructing the memory controllers to confirm that the store operations are successfully committed to the at least one persistent memory device; ensuring at the one or more memory controllers that at least all pending store operations received at the time of the request message will be committed to the persistent memory device; and sending a response message from the one or more memory controllers indicating that the store operations are successfully committed to the persistent memory device.Type: ApplicationFiled: June 29, 2013Publication date: January 1, 2015Inventors: Subramanya R. DULLOOR, Sanjay KUMAR, Rajesh M. SANKARAN, Gilbert NEIGER, Richard A. UHLIG, Robert S. CHAPPELL, Joseph NUZMAN, Kai CHENG, Sailesh KOTTAPALLI, Yen-Cheng LIU, Mohan KUMAR, Raj K. RAMANUJAN, Glenn J. HINTON
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Publication number: 20140380085Abstract: A technology for implementing a method for a machine check architecture environment. A method of the disclosure includes obtaining an occurrence of an error. The occurrence of the error causes a non-microcoded processing device to enter an error monitoring state. The method further processes the error using a dedicated memory portion for the error monitoring state while the non-microcoded processing device is in the error monitoring state. The error monitoring state is dedicated to error processing. The method further determines information associated with the error. The information associated with the error is in a predefined format.Type: ApplicationFiled: June 23, 2013Publication date: December 25, 2014Inventors: Willam C. Rash, Scott D. Hanh, Glenn J. Hinton
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Publication number: 20140351660Abstract: Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory. The far memory is presented as “main memory” to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.Type: ApplicationFiled: December 13, 2013Publication date: November 27, 2014Inventors: Eric J. DAHLEN, Glenn J. Hinton, Raj K. Ramanujan
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Patent number: RE45487Abstract: A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.Type: GrantFiled: March 14, 2013Date of Patent: April 21, 2015Assignee: Intel CorporationInventors: David J. Sager, Thomas D. Fletcher, Glenn J. Hinton, Michael D. Upton