Patents by Inventor Glenn R. Miller

Glenn R. Miller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11944113
    Abstract: Provided is a nutritionally enhanced derivative (isolate) from Stabilized Rice Bran (SRB) with improved antioxidant, fat and protein levels enhancing both the nutritional and yield values over existing techniques. Also provided is an improved method that utilizes certain enzyme combinations under various time and temperature conditions for extracting these nutritionally enhanced isolates from SRB.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: April 2, 2024
    Assignee: QJV, LLC
    Inventors: Ike E. Lynch, Glenn H. Sullivan, Larry R. Miller
  • Patent number: 11938733
    Abstract: A micro-valve includes an orifice plate having a first surface, a second surface and an orifice extending from the first surface to the second surface. An actuating beam is disposed in spaced relation to the orifice plate. The actuating beam includes a base portion and a cantilevered portion. The base portion is separated from the orifice plate by a predetermined distance. The cantilevered portion extends from the base portion such that an overlapping portion thereof overlaps the orifice. The actuating beam is movable between a closed position and an open position. The micro-valve also includes a sealing structure including a sealing member disposed at the overlapping portion of the cantilevered portion. When the actuating beam is in the closed position, the cantilevered portion is positioned such that the sealing structure seals the orifice so as to close the micro-valve.
    Type: Grant
    Filed: October 24, 2022
    Date of Patent: March 26, 2024
    Assignee: Matthews International Corporation
    Inventors: William A. Buskirk, Steven E. Flego, Charles C. Haluzak, John Whitlock, Eric R. Miller, Glenn J. T. Leighton
  • Patent number: 7008852
    Abstract: A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semiconductor material, thereby controlling electrical resistance at the interface.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: March 7, 2006
    Assignee: International Business Machines Corporation
    Inventors: Arne W. Ballantine, Douglas D. Coolbaugh, Jeffrey Gilbert, Joseph R. Greco, Glenn R. Miller
  • Patent number: 6939771
    Abstract: A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semiconductor material, thereby controlling electrical resistance at the interface.
    Type: Grant
    Filed: September 4, 2003
    Date of Patent: September 6, 2005
    Assignee: International Business Machines Corporation
    Inventors: Arne W. Ballantine, Douglas D. Coolbaugh, Jeffrey Gilbert, Joseph R. Greco, Glenn R. Miller
  • Patent number: 6822311
    Abstract: A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneously exposing the semiconductor substrate to an electric field.
    Type: Grant
    Filed: April 15, 2003
    Date of Patent: November 23, 2004
    Assignee: International Business Machines Corporation
    Inventors: Arne W. Ballantine, John J. Ellis-Monaghan, Toshihura Furukawa, Jeffrey D. Gilbert, Glenn R. Miller, James A. Slinkman
  • Publication number: 20040056327
    Abstract: A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semiconductor material, thereby controlling electrical resistance at the interface.
    Type: Application
    Filed: September 4, 2003
    Publication date: March 25, 2004
    Inventors: Arne W. Ballantine, Douglas D. Coolbaugh, Jeffrey Gilbert, Joseph R. Greco, Glenn R. Miller
  • Patent number: 6703283
    Abstract: A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semiconductor material, thereby controlling electrical resistance at the interface.
    Type: Grant
    Filed: February 4, 1999
    Date of Patent: March 9, 2004
    Assignee: International Business Machines Corporation
    Inventors: Arne W. Ballantine, Douglas D. Coolbaugh, Jeffrey Gilbert, Joseph R. Greco, Glenn R. Miller
  • Publication number: 20030201515
    Abstract: A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneously exposing the semiconductor substrate to an electric field.
    Type: Application
    Filed: April 15, 2003
    Publication date: October 30, 2003
    Applicant: International Business Machines Corporation
    Inventors: Arne W. Ballantine, John J. Ellis-Monaghan, Toshihura Furukawa, Jeffrey D. Gilbert, Glenn R. Miller, James A. Slinkman
  • Patent number: 6638629
    Abstract: A method and structure for fabricating a semiconductor wafer that may be used to monitor the temperature distribution across a wafer surface. A substrate that includes a semiconductor material and a first dopant, has an amorphous layer formed from a top portion of the substrate, and the amorphous layer is doped with a second dopant of polarity opposite to a polarity of the first dopant. Heating of the wafer at 450 to 625 degree C. recrystallizes a portion of the amorphous layer that is adjacent to the substrate at a recrystallization rate that depends on a local temperature on the wafer surface. The measured spatial distribution of sheet resistance may be utilized to readjust the spatial distribution of heat input to another wafer in order to achieve a more uniform temperature across the other wafer's surface.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: October 28, 2003
    Assignee: International Business Machines Corporation
    Inventors: Donna K. Johnson, Jerome B. Lasky, Glenn R. Miller
  • Patent number: 6552411
    Abstract: A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneously exposing the semiconductor substrate to an electric field.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: April 22, 2003
    Assignee: International Business Machines Corporation
    Inventors: Arne W. Ballantine, John J. Ellis-Monaghan, Toshihura Furukawa, Jeffrey D. Gilbert, Glenn R. Miller, James A. Slinkman
  • Publication number: 20020176998
    Abstract: A method, and associated structure, for fabricating a semiconductor wafer that may be used to monitor the temperature distribution across the wafer surface. Given a substrate that includes a semiconductor material and a first dopant, an amorphous layer is formed from a top portion of the substrate, and the amorphous layer is doped with a second dopant of polarity opposite to a polarity of the first dopant. The amorphous layer may be formed by directing an-ionic species, such as ionic germanium, into the top portion of the substrate. Alternatively, particular second dopants, such as arsenic, may serve to also amorphize the top portion of the substrate. Next, the wafer is heated to a temperature in a range of 450 to 625° C. The heating of the wafer recrystallizes a portion of the amorphous layer that is adjacent to the substrate at a recrystallization rate that depends on a local temperature on the wafer surface.
    Type: Application
    Filed: July 22, 2002
    Publication date: November 28, 2002
    Inventors: Donna K. Johnson, Jerome B. Lasky, Glenn R. Miller
  • Patent number: 6472232
    Abstract: A method, and associated structure, for fabricating a semiconductor wafer that may be used to monitor the temperature distribution across the wafer surface. Given a substrate that includes a semiconductor material and a first dopant, an amorphous layer is formed from a top portion of the substrate, and the amorphous layer is doped with a second dopant of polarity opposite to a polarity of the first dopant. The amorphous layer may be formed by directing an ionic species, such as ionic germanium, into the top portion of the substrate. Alternatively, particular second dopants, such as arsenic, may serve to also amorphize the top portion of the substrate. Next, the wafer is heated to a temperature in a range of 450 to 625° C. The heating of the wafer recrystallizes a portion of the amorphous layer that is adjacent to the substrate at a recrystallization rate that depends on a local temperature on the wafer surface.
    Type: Grant
    Filed: February 22, 2000
    Date of Patent: October 29, 2002
    Assignee: International Business Machines Corporation
    Inventors: Donna K. Johnson, Jerome B. Lasky, Glenn R. Miller
  • Publication number: 20010026999
    Abstract: A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneously exposing the semiconductor substrate to an electric field.
    Type: Application
    Filed: March 16, 2001
    Publication date: October 4, 2001
    Applicant: International Business Machines Corporation
    Inventors: Arne W. Ballantir, John J. Ellis-Monaghan, Toshihura Furukawa, Jeffrey D. Gilbert, Glenn R. Miller, James A. Slinkman
  • Patent number: 6274465
    Abstract: A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneously exposing the semiconductor substrate to a DC electric field.
    Type: Grant
    Filed: March 30, 2000
    Date of Patent: August 14, 2001
    Assignee: International Business Machines Corporataion
    Inventors: Arne W. Ballantine, John J. Ellis-Monaghan, Toshiharu Furukawa, Glenn R. Miller, James A. Slinkman