Patents by Inventor Glenn R. Miller
Glenn R. Miller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11944113Abstract: Provided is a nutritionally enhanced derivative (isolate) from Stabilized Rice Bran (SRB) with improved antioxidant, fat and protein levels enhancing both the nutritional and yield values over existing techniques. Also provided is an improved method that utilizes certain enzyme combinations under various time and temperature conditions for extracting these nutritionally enhanced isolates from SRB.Type: GrantFiled: June 8, 2021Date of Patent: April 2, 2024Assignee: QJV, LLCInventors: Ike E. Lynch, Glenn H. Sullivan, Larry R. Miller
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Patent number: 11938733Abstract: A micro-valve includes an orifice plate having a first surface, a second surface and an orifice extending from the first surface to the second surface. An actuating beam is disposed in spaced relation to the orifice plate. The actuating beam includes a base portion and a cantilevered portion. The base portion is separated from the orifice plate by a predetermined distance. The cantilevered portion extends from the base portion such that an overlapping portion thereof overlaps the orifice. The actuating beam is movable between a closed position and an open position. The micro-valve also includes a sealing structure including a sealing member disposed at the overlapping portion of the cantilevered portion. When the actuating beam is in the closed position, the cantilevered portion is positioned such that the sealing structure seals the orifice so as to close the micro-valve.Type: GrantFiled: October 24, 2022Date of Patent: March 26, 2024Assignee: Matthews International CorporationInventors: William A. Buskirk, Steven E. Flego, Charles C. Haluzak, John Whitlock, Eric R. Miller, Glenn J. T. Leighton
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Patent number: 7008852Abstract: A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semiconductor material, thereby controlling electrical resistance at the interface.Type: GrantFiled: December 2, 2004Date of Patent: March 7, 2006Assignee: International Business Machines CorporationInventors: Arne W. Ballantine, Douglas D. Coolbaugh, Jeffrey Gilbert, Joseph R. Greco, Glenn R. Miller
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Patent number: 6939771Abstract: A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semiconductor material, thereby controlling electrical resistance at the interface.Type: GrantFiled: September 4, 2003Date of Patent: September 6, 2005Assignee: International Business Machines CorporationInventors: Arne W. Ballantine, Douglas D. Coolbaugh, Jeffrey Gilbert, Joseph R. Greco, Glenn R. Miller
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Patent number: 6822311Abstract: A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneously exposing the semiconductor substrate to an electric field.Type: GrantFiled: April 15, 2003Date of Patent: November 23, 2004Assignee: International Business Machines CorporationInventors: Arne W. Ballantine, John J. Ellis-Monaghan, Toshihura Furukawa, Jeffrey D. Gilbert, Glenn R. Miller, James A. Slinkman
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Publication number: 20040056327Abstract: A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semiconductor material, thereby controlling electrical resistance at the interface.Type: ApplicationFiled: September 4, 2003Publication date: March 25, 2004Inventors: Arne W. Ballantine, Douglas D. Coolbaugh, Jeffrey Gilbert, Joseph R. Greco, Glenn R. Miller
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Patent number: 6703283Abstract: A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semiconductor material, thereby controlling electrical resistance at the interface.Type: GrantFiled: February 4, 1999Date of Patent: March 9, 2004Assignee: International Business Machines CorporationInventors: Arne W. Ballantine, Douglas D. Coolbaugh, Jeffrey Gilbert, Joseph R. Greco, Glenn R. Miller
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Publication number: 20030201515Abstract: A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneously exposing the semiconductor substrate to an electric field.Type: ApplicationFiled: April 15, 2003Publication date: October 30, 2003Applicant: International Business Machines CorporationInventors: Arne W. Ballantine, John J. Ellis-Monaghan, Toshihura Furukawa, Jeffrey D. Gilbert, Glenn R. Miller, James A. Slinkman
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Patent number: 6638629Abstract: A method and structure for fabricating a semiconductor wafer that may be used to monitor the temperature distribution across a wafer surface. A substrate that includes a semiconductor material and a first dopant, has an amorphous layer formed from a top portion of the substrate, and the amorphous layer is doped with a second dopant of polarity opposite to a polarity of the first dopant. Heating of the wafer at 450 to 625 degree C. recrystallizes a portion of the amorphous layer that is adjacent to the substrate at a recrystallization rate that depends on a local temperature on the wafer surface. The measured spatial distribution of sheet resistance may be utilized to readjust the spatial distribution of heat input to another wafer in order to achieve a more uniform temperature across the other wafer's surface.Type: GrantFiled: July 22, 2002Date of Patent: October 28, 2003Assignee: International Business Machines CorporationInventors: Donna K. Johnson, Jerome B. Lasky, Glenn R. Miller
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Patent number: 6552411Abstract: A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneously exposing the semiconductor substrate to an electric field.Type: GrantFiled: March 16, 2001Date of Patent: April 22, 2003Assignee: International Business Machines CorporationInventors: Arne W. Ballantine, John J. Ellis-Monaghan, Toshihura Furukawa, Jeffrey D. Gilbert, Glenn R. Miller, James A. Slinkman
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Publication number: 20020176998Abstract: A method, and associated structure, for fabricating a semiconductor wafer that may be used to monitor the temperature distribution across the wafer surface. Given a substrate that includes a semiconductor material and a first dopant, an amorphous layer is formed from a top portion of the substrate, and the amorphous layer is doped with a second dopant of polarity opposite to a polarity of the first dopant. The amorphous layer may be formed by directing an-ionic species, such as ionic germanium, into the top portion of the substrate. Alternatively, particular second dopants, such as arsenic, may serve to also amorphize the top portion of the substrate. Next, the wafer is heated to a temperature in a range of 450 to 625° C. The heating of the wafer recrystallizes a portion of the amorphous layer that is adjacent to the substrate at a recrystallization rate that depends on a local temperature on the wafer surface.Type: ApplicationFiled: July 22, 2002Publication date: November 28, 2002Inventors: Donna K. Johnson, Jerome B. Lasky, Glenn R. Miller
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Patent number: 6472232Abstract: A method, and associated structure, for fabricating a semiconductor wafer that may be used to monitor the temperature distribution across the wafer surface. Given a substrate that includes a semiconductor material and a first dopant, an amorphous layer is formed from a top portion of the substrate, and the amorphous layer is doped with a second dopant of polarity opposite to a polarity of the first dopant. The amorphous layer may be formed by directing an ionic species, such as ionic germanium, into the top portion of the substrate. Alternatively, particular second dopants, such as arsenic, may serve to also amorphize the top portion of the substrate. Next, the wafer is heated to a temperature in a range of 450 to 625° C. The heating of the wafer recrystallizes a portion of the amorphous layer that is adjacent to the substrate at a recrystallization rate that depends on a local temperature on the wafer surface.Type: GrantFiled: February 22, 2000Date of Patent: October 29, 2002Assignee: International Business Machines CorporationInventors: Donna K. Johnson, Jerome B. Lasky, Glenn R. Miller
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Publication number: 20010026999Abstract: A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneously exposing the semiconductor substrate to an electric field.Type: ApplicationFiled: March 16, 2001Publication date: October 4, 2001Applicant: International Business Machines CorporationInventors: Arne W. Ballantir, John J. Ellis-Monaghan, Toshihura Furukawa, Jeffrey D. Gilbert, Glenn R. Miller, James A. Slinkman
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Patent number: 6274465Abstract: A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneously exposing the semiconductor substrate to a DC electric field.Type: GrantFiled: March 30, 2000Date of Patent: August 14, 2001Assignee: International Business Machines CorporataionInventors: Arne W. Ballantine, John J. Ellis-Monaghan, Toshiharu Furukawa, Glenn R. Miller, James A. Slinkman