Abstract: The invention controls maximum average power dissipation by stalling high power instructions through the pipeline of a pipelined processor. A power dissipation controller stalls the high power instructions in order to control the processor's maximum average power dissipation. Preferably, the controller is modeled after a capacitive system with a constant output rate and a throttled input rate: the output rate represents the steady state maximum average power dissipation; while the input rate is stalled based upon current capacity, representing thermal response time. At start-up, the capacity is initialized. Yet for each high power instruction, the capacity increases by a weighted value. Each clock capacity is also decreased by a variable output rate. In particular, a low power operation is inserted to the stage execution circuit where the stall is desired, creating a low power state for that circuit. This stall effectively creates a “hole” at that pipeline stage, thus temporarily reducing power dissipation.

Abstract: An apparatus and method provide an apparatus and method for performing the addition of a PKG recoded number, to reduce noise production and power consumption. In particular, the apparatus is accomplished by a circuitry configured to receive at least two values, a first value and a second PKG value. The apparatus generates a sum value and a carry value. The method is accomplished by receiving a first value and second PKG value, and generating a sum value and a carry value from the first value and second PKG value.

Abstract: A self-timed transmission system and method are disclosed. An encoder encodes first and second data operands that are each defined on separate respective first and second sets of logic paths onto the same third set of logic paths by changing the encoding scheme. The first and second data operands are mathematically related, making this re-encoding process possible. A device, for example, a shifter, bus network, multiplexer, or buffer, processes the first and second data separately, successively in time, and in a self-timed manner, and communicates the processed first and second data onto a fourth set of logic paths. A decoder receives the processed first and second data in succession from the device on the fourth set of logic paths. The decoder decodes the first and second data onto separate respective fifth and sixth sets of logic paths, which have an encoding that corresponds to the original first and second sets of logic paths.

Abstract: The present invention generally relates to an apparatus and method for efficiently summing the partial product bits produced by a multiplier. Briefly described, in architecture, the apparatus includes a first array of odd/even summation circuitry, a second array of odd/even summation circuitry, and a linear array of adders. The apparatus is configured to add a row of partial product bits produced by a multiplier in multiplying a first operand with a second operand. The first array of odd/even summation circuitry produces a first summation of a portion of the partial product bits. The second array of odd/even circuitry produces a second summation of the other partial product bits. The linear array of adders then adds the first summation and the second summation to produce a carry save representation of a product bit (i.e., a bit of the product produced by multiplying the first operand by the second operand).

Abstract: The present transmission system disclosed herein efficiently communicates a plurality of data operands through a common digital device in a successive, self-timed manner. The transmission system is particularly suited for implementation in connection with shifting operations in a floating point (FP) fused multiply adder of a microprocessor. The transmission system includes an encoder that encodes mathematically-related first and second data operands from separate sets of paths having a first encoding scheme onto a common set of logic paths having a second encoding scheme. Further included is a device that processes the data operands successively in time and in a self-timed manner. The processed data operands are communicated to a decoder, which decodes the first and second data operands and communicates the data operands onto separate respective sets of paths having the first encoding scheme.

Abstract: A self-timed transmission system and method efficiently communicate a plurality of data operands successively through common digital device, for example, a shifter, bus network, multiplexer, or buffer, in a self-timed manner in order to minimize hardware requirements. Although not limited to this particular application, the self-timed transmission system and method are particularly suited for implementation in connection with shifting operations in a floating point (FP) fused multiply adder of a high performance microprocessor. The self-timed transmission system is constructed as follows. An encoder encodes first and second data operands that are each defined on separate respective first and second sets of logic paths onto the same third set of logic paths by changing the encoding scheme. The first and second data operands are mathematically related, making this re-encoding process possible.

Abstract: The invention controls maximum average power dissipation by stalling high power instructions through the pipeline of a pipelined processor. A power dissipation controller stalls the high power instructions in order to control the processor's maximum average power dissipation. Preferably, the controller is modeled after a capacitive system with a constant output rate and a throttled input rate: the output rate represents the steady state maximum average power dissipation; while the input rate is stalled based upon current capacity, representing thermal response time. At start-up, the capacity is initialized. Yet for each high power instruction, the capacity increases by a weighted value. Each clock capacity is also decreased by a variable output rate. In particular, a low power operation is inserted to the stage execution circuit where the stall is desired, creating a low power state for that circuit.

Abstract: A selection based rounding system and method eliminate the need for post increment based rounding in a floating point (FP) fused multiply adder that can be utilized in a processor or other digital circuit to significantly increase speed. Generally, an unincremented result and an incremented result are produced in parallel and then either one is selected as a rounded result based upon specified rounding criteria, thereby eliminating the time consuming need for an incrementor to perform rounding at or near the end of the FP fused multiply adder.

Abstract: A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.

Abstract: Circuitry for scanning and observing domino CMOS logic or other logic gates. Master and slave stages includes circuitry for latching a bit into the master stage through pulsing of a clock signal and subsequently latching the bit into the slave stage through pulsing of another clock signal. The number of transistors required for scanning is minimized by using existing latch structures within the logic.

Abstract: An apparatus and method provide an apparatus and method for reducing noise production and power consumption in a logic device that uses monotonic logic encoded signals. In particular, the apparatus is accomplished by a recode circuitry that receives and recodes a monotonic logic encoded signal received from a first logic circuit in the logic device, into a reduced switching signal. The recode circuitry sends the reduced switching signal to a second logic circuit. A decode circuitry receives and decodes the reduced switching signal back into a monotonic logic encoded signal. The decode circuitry then sends the monotonic logic encoded signal to a second logic circuit in the logic device. The method is accomplished by receiving a monotonic logic encoded signal from a first logic circuit. The monotonic logic encoded signal is converted into a reduced switching signal and transmitted. The reduced switching signal is received and converted back into the monotonic logic encoded signal.

Abstract: Method and apparatus for storing and executing an instruction to load two independent registers with two values is disclosed. In one embodiment, a computer-readable medium is encoded with an instruction including an opcode field specifying that the instruction is an instruction to load two independent registers with a first value and a second value, a source field specifying the first value and the second value, a first target register field specifying a first target register to load with the first value; a second target register field specifying a second target register to load with the second value. A system to execute the instruction is also disclosed.

Abstract: A Multiply Accumulate unit, which may be an FMAC for IEEE 754 format numbers, finds A*B±C faster if the multiplier is allowed to assume that it's A and B inputs are always positive, so that it never has to provide a complemented output, and if the C input for the accumulation with the product is also assumed to be positive. The sign magnitude notation of the IEEE 754 format is temporarily exchanged for a positive two's complement notation of the assumed positive values. Notice is taken of the actual signs, and when there is a difference to be formed, either because of addition between numbers having opposite signs, or because of a subtraction between numbers having the same sign, one of the numbers need to be negated (complemented) prior to the addition of C and the product AB. That number can always be C, provided that correct compensatory negation is available after the addition.

Abstract: A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.

Abstract: An apparatus and method provide an apparatus and method for reducing noise production and power consumption in a logic device that uses monotonic logic encoded signals. In particular, the apparatus is accomplished by a recode circuitry that receives and recodes a monotonic logic encoded signal received from a first logic circuit in the logic device, into a reduced switching signal. The recode circuitry sends the reduced switching signal to a second logic circuit. A decode circuitry receives and decodes the reduced switching signal back into a monotonic logic encoded signal. The decode circuitry then sends the monotonic logic encoded signal to a second logic circuit in the logic device. The method is accomplished by receiving a monotonic logic encoded signal from a first logic circuit. The monotonic logic encoded signal is converted into a reduced switching signal and transmitted. The reduced switching signal is received and converted back into the monotonic logic encoded signal.

Abstract: The present invention is generally directed to a system and method for supporting speculative execution of an instruction set for a central processing unit (CPU) including non-speculative and speculative instructions. In accordance with one aspect of the invention a method includes the steps of evaluating the instructions of the program to determine whether the individual instructions are speculative or non-speculative, and assessing each of the speculative instructions to determine whether it generates an exception. For each of the speculative instructions that generates an exception, the method then encode a deferred exception token (DET) into an unused register value of a register of the CPU. In accordance with another aspect of the invention, a system is provided, which system includes circuitry configured to evaluate the instructions of the instruction set to determine whether the individual instructions are speculative or non-speculative.

Abstract: An apparatus and method provide an apparatus and method for reducing noise production and power consumption in a logic device that uses traditional domino encoded signals. In particular, the apparatus is accomplished by a recode circuitry that receives and recodes a traditional domino encoded signal received from a first logic circuit in the logic device, into a reduced switching signal. The recode circuitry sends the reduced switching signal to a second logic circuit. A decode circuitry receives and decodes the reduced switching signal back into a traditional domino encoded signal. The decode circuitry then sends the traditional domino encoded signal to a second logic circuit in the logic device. The method is accomplished by receiving a traditional domino encoded signal from a first logic circuit. The traditional domino encoded signal is converted into a reduced switching signal and transmitted. The reduced switching signal is received and converted back into the traditional domino encoded signal.

Abstract: A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.

Abstract: A floating-point unit of a computer includes a floating-point computation it, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.

Abstract: The operation of a pipeline is observed by launching two or more sets of data into the pipeline on consecutive clock cycles. The clock free-runs for as many cycles as it takes the data to propagate through the stages of the pipeline. The output latches of each stage of the pipeline are only sampled when the data of interest is held in each output latch, respectively. Observation may be completely controlled through a standard test access port (TAP). Observation may be accomplished by halting the clock to scan new data in and results out, or with the clock free-running. The inputs to the pipeline may come from test registers or from circuitry which feeds the pipeline during normal operation.