Patents by Inventor Glenn Urbish
Glenn Urbish has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7351641Abstract: As disclosed herein, structures and methods are provided for forming capped chips. As provided by the disclosed method, a metal base pattern is formed on a chip insulated from wiring of the chip, and a cap is formed including a metal. The cap is joined to the metal base pattern on the chip to form the capped chip. In one embodiment, a front surface of the chip is exposed which extends from a contact of the chip to an edge of the chip. In another embodiment, a conductive connection is formed to the contact, the conductive connection extending from the contact to a terminal at an exposed plane above the front surface of the chip.Type: GrantFiled: August 11, 2005Date of Patent: April 1, 2008Assignee: Tessera, Inc.Inventors: Belgacem Haba, Masud Beroz, Glenn Urbish, David B. Tuckerman
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Patent number: 7268426Abstract: A packaged semiconductor chip includes features such as a chip carrier having a large thermal conductor which can be solder-bonded to a circuit panel so as to provide enhanced thermal conductivity to the circuit panel and electromagnetic shielding and a conductive enclosure which partially or completely surrounds the packaged chip to provide additional heat dissipation and shielding. The packaged unit may include both an active semiconductor chip and a passive element, desirably in the form of a chip, which includes resistors and capacitors. Inductors may be provided in whole or in part on the chip carrier.Type: GrantFiled: February 20, 2004Date of Patent: September 11, 2007Assignee: Tessera, Inc.Inventors: Michael Warner, Lee Smith, Belgacem Haba, Glenn Urbish, Masud Beroz, Teck-Gyu Kang
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Publication number: 20070096160Abstract: A radio frequency chip package is formed by assembling a connecting element such as a circuit board or flexible circuit tape having chips thereon with a bottom plane element such as a lead frame incorporating a large thermally-conductive plate and leads projecting upwardly from the plane of the plate. The assembly step places the rear surfaces of the chips on the bottom side of the connecting element into proximity with the thermal conductor and joins the conductive traces on the connecting element with the leads. The resulting assembly is encapsulated, leaving terminals at the bottom ends of the leads exposed. The encapsulated assembly may be surface-mounted to a circuit board. The leads provide robust electrical connections between the connecting element and the circuit board.Type: ApplicationFiled: December 18, 2006Publication date: May 3, 2007Applicant: Tessera, Inc.Inventors: Masud Beroz, Michael Warner, Lee Smith, Glenn Urbish, Teck-Gyu Kang, Jae Park, Yoichi Kubota
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Patent number: 7176506Abstract: A radio frequency chip package is formed by assembling a connecting element such as a circuit board or flexible circuit tape having chips thereon with a bottom plane element such as a lead frame incorporating a large thermally-conductive plate and leads projecting upwardly from the plane of the plate. The assembly step places the rear surfaces of the chips on the bottom side of the connecting element into proximity with the thermal conductor and joins the conductive traces on the connecting element with the leads. The resulting assembly is encapsulated, leaving terminals at the bottom ends of the leads exposed. The encapsulated assembly may be surface-mounted to a circuit board. The leads provide robust electrical connections between the connecting element and the circuit board.Type: GrantFiled: December 24, 2003Date of Patent: February 13, 2007Assignee: Tessera, Inc.Inventors: Masud Beroz, Michael Warner, Lee Smith, Glenn Urbish, Teck-Gyu Kang, Jae M. Park, Yoichi Kubota
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Publication number: 20060033189Abstract: As disclosed herein, structures and methods are provided for forming capped chips. As provided by the disclosed method, a metal base pattern is formed on a chip insulated from wiring of the chip, and a cap is formed including a metal. The cap is joined to the metal base pattern on the chip to form the capped chip. In one embodiment, a front surface of the chip is exposed which extends from a contact of the chip to an edge of the chip. In another embodiment, a conductive connection is formed to the contact, the conductive connection extending from the contact to a terminal at an exposed plane above the front surface of the chip.Type: ApplicationFiled: August 11, 2005Publication date: February 16, 2006Applicant: Tessera, Inc.Inventors: Belgacem Haba, Masud Beroz, Glenn Urbish, David Tuckerman
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Publication number: 20060013680Abstract: An array of chips spaced apart from one another by chip spacing distances, as, for example, an array of chips on a wafer dicing tape is juxtaposed with an array of chip receiving elements spaced apart from one another by receiving element spacing distances different from the chip spacing distances, as, for example, an array of substrates or fixtures spaced apart from one another at distances substantially larger than the chip spacing distances. The juxtaposing step is performed so that a set of chips including less than all of the chips in the array of chips is aligned with a set of the chip receiving elements. This set of chips is transferred to the set of chip receiving elements while the arrays are aligned with one another. The cycle may be repeated using the same or different array of chips, and using the same or different array of chip receiving elements.Type: ApplicationFiled: July 18, 2005Publication date: January 19, 2006Applicant: Tessera, Inc.Inventors: Belgacem Haba, David Tuckerman, Glenn Urbish, Masud Beroz, Ilyas Mohammed
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Publication number: 20050150813Abstract: A microelectronic fold package is formed from an in-process unit including an internal unit such as a chip and a tape defining a bottom run extending beneath the internal unit, a top run extending above the internal unit and a fold connecting said top and bottom runs. The in-process unit is engaged between a pair of elements having flat surfaces so that these elements form the top and bottom runs to a substantially flat condition at least in regions between the internal unit and the fold and so that the engagement elements form the fold to a height equal to the height of the internal unit.Type: ApplicationFiled: October 20, 2004Publication date: July 14, 2005Applicant: Tessera, Inc.Inventors: Jesse Thompson, Jennifer Alfonso, Glenn Urbish, Philip Osborn, Ellis Chau
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Publication number: 20040238934Abstract: A packaged semiconductor chip includes features such as a chip carrier having a large thermal conductor which can be solder-bonded to a circuit panel so as to provide enhanced thermal conductivity to the circuit panel and electromagnetic shielding and a conductive enclosure which partially or completely surrounds the packaged chip to provide additional heat dissipation and shielding. The packaged unit may include both an active semiconductor chip and a passive element, desirably in the form of a chip, which includes resistors and capacitors. Inductors may be provided in whole or in part on the chip carrier.Type: ApplicationFiled: February 20, 2004Publication date: December 2, 2004Applicant: Tessera, Inc.Inventors: Michael Warner, Lee Smith, Belgacem Haba, Glenn Urbish, Masud Beroz, Teck-Gyu Kang
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Publication number: 20040238857Abstract: A radio frequency chip package is formed by assembling a connecting element such as a circuit board or flexible circuit tape having chips thereon with a bottom plane element such as a lead frame incorporating a large thermally-conductive plate and leads projecting upwardly from the plane of the plate. The assembly step places the rear surfaces of the chips on the bottom side of the connecting element into proximity with the thermal conductor and joins the conductive traces on the connecting element with the leads. The resulting assembly is encapsulated, leaving terminals at the bottom ends of the leads exposed. The encapsulated assembly may be surface-mounted to a circuit board. The leads provide robust electrical connections between the connecting element and the circuit board.Type: ApplicationFiled: December 24, 2003Publication date: December 2, 2004Applicant: Tessera, Inc.Inventors: Masud Beroz, Michael Warner, Lee Smith, Glenn Urbish, Teck-Gyu Kang, Jae M. Park, Yoichi Kubota