Abstract: A intellectual property evaluation method includes the steps of receiving a plurality of input scores for each of a plurality of patents by a intellectual property management software program. The plurality of input scores are combined to form a scale value for each of the plurality of patents. The scale values are compared to determine a select group of patents. A plurality of additional information is received by the intellectual property management software program for each of the select group of patents.

Abstract: A intellectual property evaluation method includes the steps of receiving a plurality of input scores for each of a plurality of patents by a intellectual property management software program. The plurality of input scores are combined to form a scale value for each of the plurality of patents. The scale values are compared to determine a select group of patents. A plurality of additional information is received by the intellectual property management software program for each of the select group of patents.

Abstract: A programmable logic device is disclosed which contains additional circuitry allowing the architecture to be programmed. Operating as an input circuit or as an output circuit, the logical function of the device is selected to operate as a buffer, latch or register. When fabricated as a portion of a programmable logic array, the architecture is modified to the desired configuration by fusible connections which conduct normal operating current until overloaded by selective programming. Thereafter, the data path through the array is programmed in a normal fashion. The programmable architecture circuitry is readily fabricated in an integrated circuit form in conjunction with a programmable logic array.

Abstract: A circuit and a method of operation thereof are disclosed which provides an enhanced test feature for programmable logic arrays. Programmable logic arrays (PLA's) are becoming more complex and many utilize feedback into the array as part of their normal logic function. Those devices utilizing feedback require an abnormally large number of logic cycles to be run in order to provide a known feedback input into the output circuitry so that the combination of all input signals into the array is known. The preload circuit disclosed herein provides a method of applying a known signal to the feedback circuitry, thereby reducing the number of cycles required to complete a test function as well as reducing the number of pins required for the test feature. The circuit is readily fabricated in an integrated circuit form in conjunction with the PLA circuitry. The test circuitry is readily adapted to high speed automated test equipment.