Abstract: An input sensing device includes sensor pixels initialized in response to a reset signal provided through a reset line, and output a sensing signal to a read-out line in response to a scan signal provided through a scan line. A controller generates at least one start signal and clock signals. A selector selectively provides the at least one start signal and the clock signals to first control lines or second control lines. A reset driver connected to the first control lines, and supplying reset signals to at least some of the reset lines based on the at least one start signal and the clock signals provided through the first control lines. A scan driver is connected to the second control lines, and supplies scan signals to at least some of the scan lines based on the at least one start signal and the clock signals.

Abstract: The semiconductor device includes a substrate having a cell area and a via area; a transistor and a logic interconnection disposed over the substrate; a lower insulating layer covering the transistor and the logic interconnection; a lower conductive layer on the lower insulating layer in the cell area; a support pattern disposed on the lower insulating layer in the via area; a lower via plug having a side surface in contact with the support pattern and a bottom surface in contact with the logic interconnection; a word line stack disposed on the lower conductive layer in the cell area; an dielectric layer stack disposed on the support pattern in the via area; a vertical channel pillar penetrating the word line stack to be connected to the lower conductive layer; and an upper via plug penetrating the dielectric layer stack to be vertically aligned with the lower via plug.

Abstract: An input sensing device includes: sensor pixels, a horizontal driver, a selection circuit, and a vertical driver. Each of the sensor pixels is connected to a plurality of driving lines and a one of a plurality of signal input lines. The horizontal driver sequentially applies a horizontal driving signal to the sensor pixels through the driving lines. The selection circuit is connected to n of the signal input lines (n is a natural number of 2 or more) and to one output line. The selection circuit sequentially outputs n sensing signals received through the n signal input lines to the one output line. The vertical driver receives the n sensing signals through the one output line. The horizontal driver applies the horizontal driving signal n times to a given one of the driving lines to correspond to the n sensing signals.

Abstract: An input sensing device includes: sensor pixels, a horizontal driver, a selection circuit, and a vertical driver. Each of the sensor pixels is connected to a plurality of driving lines and a one of a plurality of signal input lines. The horizontal driver sequentially applies a horizontal driving signal to the sensor pixels through the driving lines. The selection circuit is connected to n of the signal input lines (n is a natural number of 2 or more) and to one output line. The selection circuit sequentially outputs n sensing signals received through the n signal input lines to the one output line. The vertical driver receives the n sensing signals through the one output line. The horizontal driver applies the horizontal driving signal n times to a given one of the driving lines to correspond to the n sensing signals.

Abstract: A semiconductor device having a three-dimensional (3D) structure is disclosed. The semiconductor device includes a first chip configured to include a peripheral circuit, and a second chip stacked on the first chip that is configured to include a first memory cell array and a second memory cell array. A plurality of transfer circuits are configured to connect a plurality of row lines of the first memory cell array and a plurality of row lines of the second memory cell array to respective global row lines is divided between the first chip and the second chip.

Abstract: A semiconductor device includes a plurality of first slits disposed at a boundary region of contiguous memory blocks isolating the memory blocks from each other, and disposed to be spaced apart from each other by a predetermined distance in a first direction; at least one word line disposed between the first slits disposed in a square shape; at least one drain selection line disposed over the word line; and a plurality of isolation patterns disposed to isolate each segment of the at least one drain selection line into units of a block. The at least one word line is integrated into a single structure.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a first slit, at least one word line, and a second slit. The first slit is disposed at a boundary between contiguous memory blocks to isolate the memory blocks from each other, and includes a first outer slit and a second outer slit, the second outer slit is spaced apart in a first direction from the first outer slit by a predetermined distance. The word line is disposed, between the first and second outer slits, including a center region having a first end and a second end, and an edge region located at the first end and a second end of the center region, and the second slit is disposed at the center region that isolate area of the word line in the center region on either side of the second slit, wherein the word line is continuous in the edge regions.

Abstract: A semiconductor device having a three-dimensional (3D) structure is disclosed. The semiconductor device includes a first chip configured to include a peripheral circuit, and a second chip stacked on the first chip that is configured to include a first memory cell array and a second memory cell array. A plurality of transfer circuits are configured to connect a plurality of row lines of the first memory cell array and a plurality of row lines of the second memory cell array to respective global row lines is divided between the first chip and the second chip.

Abstract: A semiconductor device having a three-dimensional (3D) structure is disclosed. The semiconductor device includes a first chip configured to include a logic circuit, and a second chip stacked on the first chip and configured to include a memory cell array. At least one transfer circuit for connecting a row line of the memory cell array to a global row line is distributed to each of the first chip and the second chip.

Abstract: The semiconductor device includes a substrate having a cell area and a via area; a transistor and a logic interconnection disposed over the substrate; a lower insulating layer covering the transistor and the logic interconnection; a lower conductive layer on the lower insulating layer in the cell area; a support pattern disposed on the lower insulating layer in the via area; a lower via plug having a side surface in contact with the support pattern and a bottom surface in contact with the logic interconnection; a word line stack disposed on the lower conductive layer in the cell area; an dielectric layer stack disposed on the support pattern in the via area; a vertical channel pillar penetrating the word line stack to be connected to the lower conductive layer; and an upper via plug penetrating the dielectric layer stack to be vertically aligned with the lower via plug.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a first slit, at least one word line, and a second slit. The first slit is disposed at a boundary between contiguous memory blocks to isolate the memory blocks from each other, and includes a first outer slit and a second outer slit, the second outer slit is spaced apart in a first direction from the first outer slit by a predetermined distance. The word line is disposed, between the first and second outer slits, including a center region having a first end and a second end, and an edge region located at the first end and a second end of the center region, and the second slit is disposed at the center region that isolate area of the word line in the center region on either side of the second slit, wherein the word line is continuous in the edge regions.

Abstract: A semiconductor device having a three-dimensional (3D) structure is disclosed. The semiconductor device includes a first chip configured to include a logic circuit, and a second chip stacked on the first chip and configured to include a memory cell array. At least one transfer circuit for connecting a row line of the memory cell array to a global row line is distributed to each of the first chip and the second chip.

Abstract: A semiconductor memory device includes a circuit chip including a first substrate, peripheral circuit elements which are defined on the first substrate and a first dielectric layer which covers the peripheral circuit elements, and having first pads which are coupled to the peripheral circuit elements, on one surface thereof; a memory chip including a second substrate which is disposed on a base dielectric layer, a memory cell array which is defined on the second substrate and a second dielectric layer which covers the memory cell array, and having second pads which are coupled with the first pads, on one surface thereof which is bonded with the one surface of the circuit chip; a contact passing through the base dielectric layer and the second dielectric layer; and one or more dummy contacts passing through the base dielectric layer and the second dielectric layer, and disposed around the contact.

Abstract: A semiconductor memory device mc des a substrate defined with cell regions and a contact region between the cell regions; a dielectric structure formed over the contact region; a memory block having cell parts which are respectively formed over the cell regions, a coupling part which is formed over the contact region and couples the cell parts, and a through part which accommodates the dielectric structure; a peripheral circuit formed over the substrate under the memory block; bottom wiring lines disposed between the memory block and the peripheral circuit, and electrically coupled with the peripheral circuit; top wiring lines disposed over the memory block; and contact plugs passing through the dielectric structure and coupling the bottom wiring lines and the top wiring lines.

Abstract: A semiconductor memory device includes a circuit chip including a first substrate, peripheral circuit elements which are defined on the first substrate and a first dielectric layer which covers the peripheral circuit elements, and having first pads which are coupled to the peripheral circuit elements, on one surface thereof; a memory chip including a second substrate which is disposed on a base dielectric layer, a memory cell array which is defined on the second substrate and a second dielectric layer which covers the memory cell array, and having second pads which are coupled with the first pads, on one surface thereof which is bonded with the one surface of the circuit chip; a contact passing through the base dielectric layer and the second dielectric layer; and one or more dummy contacts passing through the base dielectric layer and the second dielectric layer, and disposed around the contact.

Abstract: A semiconductor memory device includes a peripheral circuit region including a first substrate, a peripheral circuit element disposed at least partially over the first substrate, a first dielectric layer covering the peripheral circuit element and a bottom wiring line disposed in the first dielectric layer and electrically coupled to the peripheral circuit element; a cell region including a second substrate disposed over the first dielectric layer, a memory cell array disposed over the second substrate; a second dielectric layer covering the memory cell array; a contact coupled to the bottom wiring line by passing through the second dielectric layer and the first dielectric layer in a first direction perpendicular to a top surface of the second substrate; and at least one dummy contact disposed adjacent to the contact in the second dielectric layer.

Abstract: A semiconductor memory device includes a peripheral circuit region including a first substrate, a peripheral circuit element disposed at least partially over the first substrate, a first dielectric layer covering the peripheral circuit element and a bottom wiring line disposed in the first dielectric layer and electrically coupled to the peripheral circuit element; a cell region including a second substrate disposed over the first dielectric layer, a memory cell array disposed over the second substrate; a second dielectric layer covering the memory cell array; a contact coupled to the bottom wiring line by passing through the second dielectric layer and the first dielectric layer in a first direction perpendicular to a top surface of the second substrate; and at least one dummy contact disposed adjacent to the contact in the second dielectric layer.

Abstract: A semiconductor memory device mc des a substrate defined with cell regions and a contact region between the cell regions; a dielectric structure formed over the contact region; a memory block having cell parts which are respectively formed over the cell regions, a coupling part which is formed over the contact region and couples the cell parts, and a through part which accommodates the dielectric structure; a peripheral circuit formed over the substrate under the memory block; bottom wiring lines disposed between the memory block and the peripheral circuit, and electrically coupled with the peripheral circuit; top wiring lines disposed over the memory block; and contact plugs passing through the dielectric structure and coupling the bottom wiring lines and the top wiring lines.

Abstract: A semiconductor memory device includes a substrate defined with cell regions and a contact region between the cell regions; a dielectric structure formed over the contact region; a memory block having cell parts which are respectively formed over the cell regions, a coupling part which is formed over the contact region and couples the cell parts, and a through part which accommodates the dielectric structure; a peripheral circuit formed over the substrate under the memory block; bottom wiring lines disposed between the memory block and the peripheral circuit, and electrically coupled with the peripheral circuit; top wiring lines disposed over the memory block; and contact plugs passing through the dielectric structure and coupling the bottom wiring lines and the top wiring lines.

Abstract: A semiconductor memory device includes a substrate defined with cell regions and a contact region between the cell regions; a dielectric structure formed over the contact region; a memory block having cell parts which are respectively formed over the cell regions, a coupling part which is formed over the contact region and couples the cell parts, and a through part which accommodates the dielectric structure; a peripheral circuit formed over the substrate under the memory block; bottom wiring lines disposed between the memory block and the peripheral circuit, and electrically coupled with the peripheral circuit; top wiring lines disposed over the memory block; and contact plugs passing through the dielectric structure and coupling the bottom wiring lines and the top wiring lines.