Patents by Inventor Gobi R. Padmanabhan

Gobi R. Padmanabhan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8288834
    Abstract: Various semiconductor devices can be formed at the end of a common fabrication process, thereby significantly improving manufacturing flexibility, by selectively wiring bonding different CMOS circuits to different MEMS, which are formed on the same semiconductor die. A semiconductor device that has a number of CMOS circuits and a number of MEMS is formed on the same semiconductor wafer in adjacent regions on the wafer, and then diced such that the CMOS circuits and the MEMS are formed on the same die. After dicing, different CMOS circuits and different MEMS can be selectively connected during the wire bonding step to form the different semiconductor devices.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: October 16, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Gobi R. Padmanabhan, Visvamohan Yegnashankaran
  • Patent number: 7790602
    Abstract: A method of forming capacitive structures in trenches which have been formed in a multilevel metal interconnect structure is disclosed. The method of forming the capacitive structures allows the capacitance of the multilevel metal interconnect structure to be adjusted, and thereby optimized, to respond to signals from devices that are formed on an underlying substrate.
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: September 7, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Visvamohan Yegnashankaran, Gobi R. Padmanabhan
  • Patent number: 7633131
    Abstract: A semiconductor sensor device is formed using MEMS technology by placing a thin layer of single-crystal silicon, which includes semiconductor devices, over a cavity, which has been formed in a semiconductor material. The thin layer of single-crystal silicon can be formed by forming the semiconductor devices in the top surface of a single-crystal silicon wafer, thinning the silicon wafer to a desired thickness, and then dicing the thinned wafer to form silicon layers of a desired size. The MEMS device can be used to implement a pressure sensor, microphone, temperature sensor, and a joystick.
    Type: Grant
    Filed: February 1, 2007
    Date of Patent: December 15, 2009
    Assignee: National Semiconductor Corporation
    Inventors: Gobi R. Padmanabhan, Visvamohan Yegnashankaran
  • Patent number: 7482228
    Abstract: The width of the gate of a MOS transistor can be formed to have nanometer-width gate sizes, which are substantially less than the minimum feature size that can be photolithographically obtained with the method that is used to fabricate the MOS transistors, in a litho-less process by utilizing a conductive side wall spacer to form the gate of the MOS transistor.
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: January 27, 2009
    Assignee: National Semiconductor Corporation
    Inventors: Gobi R. Padmanabhan, Visvamohan Yegnashankaran
  • Patent number: 7399274
    Abstract: The present invention provides a capsule endoscope (CE) having sensors configured to form or to conform to the shell of the CE. The sensors are curved to correspond to the capsule's shape. According to this embodiment, the sensors may be covered by a coating material to protect the sensors. The sensors may also form the capsule shell. Instead of being covered by a shell associated with the capsule, the sensors are formed as the capsule shell. The sensors may also form part of the capsule shell. For example, one half of the capsule shell may be formed from the sensors.
    Type: Grant
    Filed: August 19, 2003
    Date of Patent: July 15, 2008
    Assignee: National Semiconductor Corporation
    Inventors: Brian Lester Halla, Joseph Domenick Montalbo, Gobi R. Padmanabhan, Peter Yi-Ning Wang
  • Patent number: 7338840
    Abstract: Thermal hot spots in the substrate of a semiconductor die, and the required surface area of the semiconductor die, are substantially reduced by forming thermal or thermal and electrical pipes in the substrate that extend from a bottom surface of the substrate to a point near the top surface of the substrate.
    Type: Grant
    Filed: May 17, 2006
    Date of Patent: March 4, 2008
    Assignee: National Semiconductor Corporation
    Inventors: Gobi R. Padmanabhan, Visvamohan Yegnashankaran
  • Patent number: 7329555
    Abstract: Various semiconductor devices can be formed at the end of a common fabrication process, thereby significantly improving manufacturing flexibility, by selectively wiring bonding different CMOS circuits to different MEMS, which are formed on the same semiconductor die. A semiconductor device that has a number of CMOS circuits and a number of MEMS is formed on the same semiconductor wafer in adjacent regions on the wafer, and then diced such that the CMOS circuits and the MEMS are formed on the same die. After dicing, different CMOS circuits and different MEMS can be selectively connected during the wire bonding step to form the different semiconductor devices.
    Type: Grant
    Filed: July 20, 2004
    Date of Patent: February 12, 2008
    Assignee: National Semiconductor Corporation
    Inventors: Gobi R. Padmanabhan, Visvamohan Yegnashankaran
  • Patent number: 7230301
    Abstract: A resistor, a transistor, and a capacitor can be fabricated on a semiconductor wafer in a process that forms an isolated single-crystal region with precise dimensions. The isolated single-crystal region, in turn, defines the body of the resistor, the gate of the transistor, and the top plate of the capacitor.
    Type: Grant
    Filed: July 6, 2004
    Date of Patent: June 12, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Gobi R. Padmanabhan, Visvamohan Yegnashankaran
  • Patent number: 7192819
    Abstract: A semiconductor sensor device is formed using MEMS technology by placing a thin layer of single-crystal silicon, which includes semiconductor devices, over a cavity, which has been formed in a semiconductor material. The thin layer of single-crystal silicon can be formed by forming the semiconductor devices in the top surface of a single-crystal silicon wafer, thinning the silicon wafer to a desired thickness, and then dicing the thinned wafer to form silicon layers of a desired size. The MEMS device can be used to implement a pressure sensor, microphone, temperature sensor, and a joystick.
    Type: Grant
    Filed: July 20, 2004
    Date of Patent: March 20, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Gobi R. Padmanabhan, Visvamohan Yegnashankaran
  • Patent number: 7109571
    Abstract: A semiconductor die is formed in a process that forms a trench opening in the semiconductor material prior to the formation of the contacts and the metal-1 layer. When contacts are then formed to contact circuit structures, such as a doped region in the top surface of the semiconductor material, a trench contact is formed that fills up the trench opening. During the final steps of the process, the back side of the semiconductor material is ground down to expose the trench contact. The wafer is cut to form a plurality of dice, and the exposed edges of the dice are protected.
    Type: Grant
    Filed: April 26, 2004
    Date of Patent: September 19, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Gobi R. Padmanabhan, Visvamohan Yegnashankaran
  • Patent number: 7075133
    Abstract: Thermal hot spots in the substrate of a semiconductor die, and the required surface area of the semiconductor die, are substantially reduced by forming thermal or thermal and electrical pipes in the substrate that extend from a bottom surface of the substrate to a point near the top surface of the substrate.
    Type: Grant
    Filed: May 3, 2004
    Date of Patent: July 11, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Gobi R. Padmanabhan, Visvamohan Yegnashankaran
  • Patent number: 7052977
    Abstract: A semiconductor wafer is diced utilizing a method that etches down to the top surface of the semiconductor wafer a number of times, such as during and following the formation of the metal interconnect structure, and then thins the semiconductor wafer from the back side until the semiconductor wafer singulates.
    Type: Grant
    Filed: July 6, 2004
    Date of Patent: May 30, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Visvamohan Yegnashankaran, Gobi R. Padmanabhan
  • Patent number: 7044908
    Abstract: A capsule endoscope (CE) having a field of view that may be dynamically adjusted. The CE includes an illuminator that may be an optical or acoustical illuminator designed to illuminate the lining of a GI tract. A scanner, such as a MEMS scanner may be used to scan the illumination source onto the lining. The scanner may be controlled to dynamically adjust the field of view. A lenslet array may also be used to focus the illumination. The sensor is formed such that it may be curved to a contour and includes a support having sufficient flexibility such that it can be formed to the contour. The substrate includes the sensor and is formed sufficiently thin so that it can be shaped to the contour. The substrate is coupled with the support such that the combination can be formed to the contour.
    Type: Grant
    Filed: July 8, 2003
    Date of Patent: May 16, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Joseph Domenick Montalbo, Gobi R. Padmanabhan
  • Patent number: 7042092
    Abstract: The capacitance of a multilevel metal interconnect formed on a semiconductor substrate can be adjusted, and thereby optimized, to respond to signals from devices that are formed on the underlying substrate by forming capacitive structures in trenches which have been formed using the top metal layer as a mask.
    Type: Grant
    Filed: December 5, 2001
    Date of Patent: May 9, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Visvamohan Yegnashankaran, Gobi R. Padmanabhan
  • Patent number: 6949421
    Abstract: A vertical MOS transistor has a very short channel length that is indirectly defined by the thickness of a layer of semiconductor material or the depths of implants. The transistor has a first (source/drain) region formed in a substrate material, a semiconductor region formed on the first region, and a second (source/drain) region formed in the top surface of the semiconductor region. The distance between the first region and the second region defines the channel length of the transistor.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: September 27, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Gobi R. Padmanabhan, Visvamohan Yegnashankaran
  • Patent number: 6946321
    Abstract: A semiconductor integrated circuit with high Q inductors and capacitors is disclosed. A semiconductor electrical circuit is formed on a first die, while micro-electromechanical structures having inductance and capacitance are formed on a second die. The second die is attached and electrically connected to the first die as a flip chip.
    Type: Grant
    Filed: May 26, 2004
    Date of Patent: September 20, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Visvamohan Yegnashankaran, Gobi R. Padmanabhan
  • Patent number: 6833781
    Abstract: An inductor is formed from the interconnect structure of a semiconductor chip, using the vias and metal regions to form up and down segments of a loop, and horizontal metal lines to form the top and bottom segments of the loop. In addition, a second inductor can be formed between or under the first inductor to form an inductive system, such as a transformer.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: December 21, 2004
    Assignee: National Semiconductor Corporation
    Inventors: Gobi R. Padmanabhan, Visvamohan Yegnashankaran
  • Patent number: 6781239
    Abstract: A semiconductor integrated circuit with high Q inductors and capacitors is disclosed. A semiconductor electrical circuit is formed on a first die, while micro-electromechanical structures having inductance and capacitance are formed on a second die. The second die is attached and electrically connected to the first die as a flip chip.
    Type: Grant
    Filed: December 5, 2001
    Date of Patent: August 24, 2004
    Assignee: National Semiconductor Corporation
    Inventors: Visvamohan Yegnashankaran, Gobi R. Padmanabhan
  • Patent number: 6777288
    Abstract: A vertical MOS transistor has a very short channel length that is indirectly defined by the thickness of a layer of semiconductor material or the depths of implants. The transistor has a first (source/drain) region formed in a substrate material, a semiconductor region formed on the first region, and a second (source/drain) region formed in the top surface of the semiconductor region. The distance between the first region and the second region defines the channel length of the transistor.
    Type: Grant
    Filed: November 6, 2002
    Date of Patent: August 17, 2004
    Assignee: National Semiconductor Corporation
    Inventors: Gobi R. Padmanabhan, Visvamohan Yegnashankaran
  • Patent number: 6746956
    Abstract: A semiconductor die is formed in a process that forms a trench opening in the semiconductor material prior to the formation of the contacts and the metal-1 layer. When contacts are then formed to contact circuit structures, such as a doped region in the top surface of the semiconductor material, a trench contact is formed that fills up the trench opening. During the final steps of the process, the back side of the semiconductor material is ground down to expose the trench contact. The wafer is cut to form a plurality of dice, and the exposed edges of the dice are protected.
    Type: Grant
    Filed: June 13, 2002
    Date of Patent: June 8, 2004
    Assignee: National Semiconductor Corporation
    Inventors: Gobi R. Padmanabhan, Visvamohan Yegnashankaran