Abstract: A method for controlling the power used by a computer including the steps of measuring the operating characteristics of a central processor of the computer, determining when the operating characteristics of the central processor are significantly different than required by the operations being conducted, and changing the operating characteristics of the central processor to a level commensurate with the operations being conducted.

Abstract: A gated store buffer including circuitry for temporarily holding apart from other memory stores all memory stores sequentially generated during a translation interval by a host processor translating a sequence of target instructions into host instructions, circuitry for transferring memory stores sequentially generated during a translation interval to memory if the translation executes without generating an exception, circuitry for indicating which memory stores to identical memory addresses are most recent in response to a memory access at the memory address, and circuitry for eliminating memory stores sequentially generated during a translation interval if the translation executes without generating an exception.

Abstract: A dynamic clocked inverter latch with reduced charge leakage includes a first node biasing circuit with a P-MOSFET and an N-MOSFET totem-pole-coupled between VDD and an output node, and a second node biasing circuit with another N-MOSFET and another P-MOSFET totem-pole-coupled between the output node and VSS. The first P-MOSFET receives an input data signal and the first N-MOSFET receives a clock signal and in accordance therewith together cause the output node to charge to a charged state having a charge voltage associated therewith. The second N-MOSFET also receives the input data signal while the second P-MOSFET receives the inverse of the clock signal and in accordance therewith together cause the output node to discharge to a discharged state having a discharge voltage associated therewith.

Abstract: An arithmetic logic unit (ALU) with improved critical path performance includes two sets of adder circuits, a logic circuit, a set of multiplexors and a decoder. The adder circuits perform redundant add operations, one with a unit carry input and one without a carry input, upon multiple respective portions of the two sets of input signal bits. The logic circuit performs Boolean logic operations upon the two sets of input signal bits. In accordance with a set of selection control signals, the multiplexors select among the multiple results of such redundant add operations and Boolean logical operations for outputting as the final output bits. Such selection control signals are generated by the decoder based upon the contents of the two sets of input signal bits.

Abstract: A dynamic clocked inverter latch with reduced charge leakage includes a first node biasing circuit with a P-MOSFET and an N-MOSFET totem-pole-coupled between VDD and an output node, and a second node biasing circuit with another N-MOSFET and another P-MOSFET totem-pole-coupled between the output node and VSS. The first P-MOSFET receives an input data signal and the first N-MOSFET receives a clock signal and in accordance therewith together cause the output node to charge to a charged state having a charge voltage associated therewith. The second N-MOSFET also receives the input data signal while the second P-MOSFET receives the inverse of the clock signal and in accordance therewith together cause the output node to discharge to a discharged state having a discharge voltage associated therewith.

Abstract: A storage cell includes a first bit line, a storage circuit, and a pass transistor. The storage circuit has a first storage node for holding a logic state indicative of a logic value. The pass transistor is coupled to the first bit line and the first storage node for establishing a conduction path therebetween. The pass transistor receives a bias voltage to switch the pass transistor into a substantially nonconducting state when the storage cell is not being accessed. The reverse bias on the first transistor substantially reduces the leakage current through the pass transistor.

Abstract: A data latch with reduced data signal leakage includes a latch circuit and a clock buffer circuit which provides a differential clock signal to the input transmission gate of the latch circuit. The clock buffer circuit is biased between upper and lower supply voltage potentials which are higher and lower, respectively, than those between which the latch circuit is biased. This causes the differential clock signal to be overdriven with respect to the incoming data signal which is latched by the latch circuit. As a result, the input transmission gate of the latch circuit is reverse-biased during the inactive state of the differential clock signal, thereby isolating the storage node within the latch circuit and preventing signal leakage therefrom.

Abstract: A circuit for reducing current leakage in a logic circuit such as a write driver circuit in a memory array is disclosed. The current leakage reducing circuit includes a data line configured to be set to a predetermined voltage, a data drive circuit, and an enable circuit. The enable circuit is coupled to the data line and the data drive circuit, and is configured to enable the data line to accept a data value from the data drive circuit. The invention also includes a current leakage prevention circuit, coupled to the enable circuit, and configured to substantially reduce leakage from the data line through the enable circuit when the enable circuit is not enabled.

Abstract: A logic and memory circuit with reduced input-to-output signal propagation delay includes signal processor and memory elements connected in parallel for performing "memory work" simultaneously with "logical work" and/or "electrical work." Incorporated within a flip-flop having master and slave latches which perform the memory work (i.e. data storage) on the input and output logic signals, respectively, is a signal processor which processes one or more input signals to provide an output signal. Where memory work and electrical work are to be performed simultaneously, the signal processor includes a serial group of circuits having successively larger transistors for buffering an input signal to provide the output signal simultaneously with the storage of the input and output signals by the master and slave latches, respectively. Where memory work and logical work are to be performed simultaneously, the signal processor includes a logic function circuit (e.g.

Abstract: A static logic circuit with improved output signal levels includes a static complementary MOSFET circuit with a signal node and pull-up and pull-down amplifiers, each with at least one biasing circuit, connected thereto. The pull-up and pull-down amplifiers are connected to VDD and VSS, respectively, and receive one or more logic signals (e.g. one for an inverter and more for logic gates such as AND, OR, etc.) and one or more bias signals and in accordance therewith provide pull-up and pull-down voltages, respectively, to the signal node. In accordance with the applied pull-up or pull-down voltage, the signal node charges to a charge state with an associated node voltage approximately equal to VDD or VSS, respectively. Each biasing circuit receives the same input logic signal as its associated pull-up or pull-down amplifier and provides thereto a bias signal approximately equal to VSS or VDD, respectively.

Abstract: A dynamic logic circuit with reduced charge leakage includes a dynamic complementary MOSFET logic circuit with a P-type MOSFET, a number of N-type MOSFETs and a static CMOSFET inverter circuit. In response to a low clock signal, the P-type MOSFET turns on and charges the precharge node to a precharged node voltage. Some of the N-type MOSFETs are interconnected to form a logic circuit to logically process incoming logic signals and in accordance therewith selectively provide a conduction path for electrical charges from the precharge node. In response to a high clock signal, another N-type MOSFET turns on and together with the logic circuit conditionally discharges the precharge node via the logic circuit conduction path to a discharged node voltage. The value of the discharged node voltage is intermediate to the precharged node voltage and the circuit reference node voltage (e.g. VSS=0). The inverter circuit inverts and buffers the precharged and discharged node voltages.

Abstract: A storage cell includes a first bit line, a storage circuit, and a pass transistor. The storage circuit has a first storage node for holding a logic state indicative of a logic value. The pass transistor is coupled to the first bit line and the first storage node for establishing a conduction path therebetween. The pass transistor receives a bias voltage to switch the pass transistor into a substantially nonconducting state when the storage cell is not being accessed. The reverse bias on the first transistor substantially reduces the leakage current through the pass transistor.

Abstract: A delay compensator circuit is disclosed to compensate for variations in temperature, supply voltage and process. A monitor circuit is further disclosed that allows the monitoring of the delay of a delay element. The delay compensator circuit and monitor circuit lend themselves easily to the ASIC design methodology since they use conventional ASIC building blocks; namely gates, memory elements and delay elements. The delay compensator and monitor use a time base to track variations in circuit parameters by monitoring the delay through a delay element (delay line or sub-circuit). Compensation may be achieved by switching delays in or out of the circuit to be compensated based on variations of temperature, voltage, and process as measured using the time base. The delay compensator permits the designer to control the output hold time independently of the output delay time. The delay compensator enables a latching device to hold the output signal for the required duration after a reference.