Patents by Inventor Godwin Gerald Arulappan
Godwin Gerald Arulappan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11747885Abstract: Disclosed are techniques for saving power in a Universal Serial Bus (USB) repeater/re-timer between a USB host and a peripheral device by intercepting packets received from the host to predict the direction of data traffic to selectively turn off/on circuitry of a peripheral port used to receive packets from the peripheral device. If a host port determines that the host is sending a start-of-frame (SOF) packet, the direction of data flow is from the host to the peripheral device, and the repeater may turn off the peripheral port such as squelch circuitry. If the host port determines that the host is sending a non-SOF packet, such as an address token that precedes a host-to-peripheral-device data transfer or a peripheral-device-to-host data transfer, the direction of data flow is anticipated to be from the peripheral device to the host, and the repeater may re-enable the deactivated circuitry of the peripheral port.Type: GrantFiled: November 17, 2022Date of Patent: September 5, 2023Assignee: Cypress Semiconductor CorporationInventors: Pradeep Kumar Bajpai, Godwin Gerald Arulappan, Anup Nayak
-
Patent number: 11728930Abstract: Disclosed are techniques to regenerate SYNC bits of a High-Speed data packet lost by the transmission envelope detector of a repeater/hub that interconnects electronic devices compliant with Universal Serial Bus (USB) Specification Revision 2.0 or higher. A physical layer logic (PHY) of a first port of the repeater/hub receives a High-Speed data packet to store a recovered bit stream into an elastic buffer. The recovered bit stream may lose some SYNC bits at the beginning of the SYNC pattern. The repeater/hub reads the recovered bit stream from the elastic buffer for transmission through the PHY of a second port. If the end of the SYNC is read before a programmable number of SYNC bits have been transmitted, the repeater/hub generates additional SYNC bits for transmission until the programmable number of SYNC bits are transmitted. The repeater/hub then resumes transmitting the rest of the High-Speed data packet starting from the payload.Type: GrantFiled: December 7, 2022Date of Patent: August 15, 2023Assignee: Cypress Semiconductor CorporationInventors: Godwin Gerald Arulappan, Pradeep Kumar Bajpai
-
Publication number: 20230099199Abstract: Disclosed are techniques to regenerate SYNC bits of a High-Speed data packet lost by the transmission envelope detector of a repeater/hub that interconnects electronic devices compliant with Universal Serial Bus (USB) Specification Revision 2.0 or higher. A physical layer logic (PHY) of a first port of the repeater/hub receives a High-Speed data packet to store a recovered bit stream into an elastic buffer. The recovered bit stream may lose some SYNC bits at the beginning of the SYNC pattern. The repeater/hub reads the recovered bit stream from the elastic buffer for transmission through the PHY of a second port. If the end of the SYNC is read before a programmable number of SYNC bits have been transmitted, the repeater/hub generates additional SYNC bits for transmission until the programmable number of SYNC bits are transmitted. The repeater/hub then resumes transmitting the rest of the High-Speed data packet starting from the payload.Type: ApplicationFiled: December 7, 2022Publication date: March 30, 2023Applicant: Cypress Semiconductor CorporationInventors: Godwin Gerald ARULAPPAN, Pradeep Kumar BAJPAI
-
Publication number: 20230081229Abstract: Disclosed are techniques for saving power in a Universal Serial Bus (USB) repeater/re-timer between a USB host and a peripheral device by intercepting packets received from the host to predict the direction of data traffic to selectively turn off/on circuitry of a peripheral port used to receive packets from the peripheral device. If a host port determines that the host is sending a start-of-frame (SOF) packet, the direction of data flow is from the host to the peripheral device, and the repeater may turn off the peripheral port such as squelch circuitry. If the host port determines that the host is sending a non-SOF packet, such as an address token that precedes a host-to-peripheral-device data transfer or a peripheral-device-to-host data transfer, the direction of data flow is anticipated to be from the peripheral device to the host, and the repeater may re-enable the deactivated circuitry of the peripheral port.Type: ApplicationFiled: November 17, 2022Publication date: March 16, 2023Applicant: Cypress Semiconductor CorporationInventors: Pradeep Kumar Bajpai, Godwin Gerald Arulappan, Anup Nayak
-
Patent number: 11528095Abstract: Disclosed are techniques for removing dribble bits following the end-of-packet (EOP) of a High-Speed data packet inserted by the transmission envelope detector of a repeater/hub that interconnects electronic devices compliant with Universal Serial Bus (USB) Specification Revision 2.0 or higher. A physical layer logic (PHY) of a first port of the repeater/hub receives a High-Speed data packet to store a recovered bit stream into an elastic buffer. The recovered bit stream may include dribble bits inserted by the PHY after the EOP. The repeater/hub reads the recovered bit stream from the elastic buffer for transmission through the PHY of a second port. The repeater/hub monitors the EOP. When the EOP is detected, the repeater/hub prevents transmission of the dribble bits of the recovered bit stream following the EOP from the second port, eliminating the intended receiver of the High-Speed data packet from the complexity of dealing with dribble bits.Type: GrantFiled: December 11, 2020Date of Patent: December 13, 2022Assignee: Cypress Semiconductor CorporationInventors: Godwin Gerald Arulappan, Pradeep Kumar Bajpai
-
Patent number: 11513584Abstract: Disclosed are techniques for saving power in a Universal Serial Bus (USB) repeater/re-timer between a USB host and a peripheral device by intercepting packets received from the host to predict the direction of data traffic to selectively turn off/on circuitry of a peripheral port used to receive packets from the peripheral device. If a host port determines that the host is sending a start-of-frame (SOF) packet, the direction of data flow is from the host to the peripheral device, and the repeater may turn off the peripheral port such as squelch circuitry. If the host port determines that the host is sending a non-SOF packet, such as an address token that precedes a host-to-peripheral-device data transfer or a peripheral-device-to-host data transfer, the direction of data flow is anticipated to be from the peripheral device to the host, and the repeater may re-enable the deactivated circuitry of the peripheral port.Type: GrantFiled: March 4, 2021Date of Patent: November 29, 2022Assignee: Cypress Semiconductor CorporationInventors: Pradeep Kumar Bajpai, Godwin Gerald Arulappan, Anup Nayak
-
Publication number: 20220283624Abstract: Disclosed are techniques for saving power in a Universal Serial Bus (USB) repeater/re-timer between a USB host and a peripheral device by intercepting packets received from the host to predict the direction of data traffic to selectively turn off/on circuitry of a peripheral port used to receive packets from the peripheral device. If a host port determines that the host is sending a start-of-frame (SOF) packet, the direction of data flow is from the host to the peripheral device, and the repeater may turn off the peripheral port such as squelch circuitry. If the host port determines that the host is sending a non-SOF packet, such as an address token that precedes a host-to-peripheral-device data transfer or a peripheral-device-to-host data transfer, the direction of data flow is anticipated to be from the peripheral device to the host, and the repeater may re-enable the deactivated circuitry of the peripheral port.Type: ApplicationFiled: March 4, 2021Publication date: September 8, 2022Applicant: Cypress Semiconductor CorporationInventors: Pradeep Kumar Bajpai, Godwin Gerald Arulappan, Anup Nayak
-
Publication number: 20220190960Abstract: Disclosed are techniques for removing dribble bits following the end-of-packet (EOP) of a High-Speed data packet inserted by the transmission envelope detector of a repeater/hub that interconnects electronic devices compliant with Universal Serial Bus (USB) Specification Revision 2.0 or higher. A physical layer logic (PHY) of a first port of the repeater/hub receives a High-Speed data packet to store a recovered bit stream into an elastic buffer. The recovered bit stream may include dribble bits inserted by the PHY after the EOP. The repeater/hub reads the recovered bit stream from the elastic buffer for transmission through the PHY of a second port. The repeater/hub monitors the EOP. When the EOP is detected, the repeater/hub prevents transmission of the dribble bits of the recovered bit stream following the EOP from the second port, eliminating the intended receiver of the High-Speed data packet from the complexity of dealing with dribble bits.Type: ApplicationFiled: December 11, 2020Publication date: June 16, 2022Applicant: Cypress Semiconductor CorporationInventors: Godwin Gerald Arulappan, Pradeep Kumar Bajpai
-
Patent number: 11262827Abstract: In an example embodiment, a Universal Serial Bus (USB) Type-C cable comprises a USB Type-C connector and an IC controller coupled thereto. The IC controller comprises a terminal coupled to a VCONN line of the USB Type-C cable, a transistor coupled between the terminal and an internal power supply of the IC controller, a resistive element coupled between the terminal and a control terminal of the transistor, and control logic. The IC controller is to: power on the transistor from a voltage, received at the terminal, falling across the resistive element; power on the internal power supply in response to the voltage being passed through the transistor; power up the IC controller in response to powering on the internal power supply; and operate the control logic to fully power on the transistor, and thus enter an active mode of the IC controller.Type: GrantFiled: July 1, 2020Date of Patent: March 1, 2022Assignee: Cypress Semiconductor CorporationInventors: Nicholas Alexander Bodnaruk, Pradeep Kumar Bajpai, Godwin Gerald Arulappan, Hamid Khodabandehlou
-
Publication number: 20200409440Abstract: In an example embodiment, a Universal Serial Bus (USB) Type-C cable comprises a USB Type-C connector and an IC controller coupled thereto. The IC controller comprises a terminal coupled to a VCONN line of the USB Type-C cable, a transistor coupled between the terminal and an internal power supply of the IC controller, a resistive element coupled between the terminal and a control terminal of the transistor, and control logic. The IC controller is to: power on the transistor from a voltage, received at the terminal, falling across the resistive element power on the internal power supply in response to the voltage being passed through the transistor; power up the IC controller in response to powering on the internal power supply; and operate the control logic to fully power on the transistor, and thus enter an active mode of the IC controller.Type: ApplicationFiled: July 1, 2020Publication date: December 31, 2020Applicant: Cypress Semiconductor CorporationInventors: Nicholas Alexander Bodnaruk, Pradeep Kumar Bajpai, Godwin Gerald Arulappan, Hamid Khodabandehlou
-
Patent number: 10719112Abstract: A semiconductor device for a USB Type-C cable includes a first terminal to couple to a first VCONN line from a first end of the cable, a second terminal to couple to a second VCONN line from the second end of the cable, a charge pump, and a switch circuit coupled to the first terminal and the second terminal. The switch circuit includes a first drain-extended n-type field effect transistor (DENFET) coupled between the first terminal and an internal power supply of the semiconductor device; a first pump switch coupled between the charge pump and a gate of the first DENFET; a second DENFET coupled between the second terminal and the internal power supply; and a second pump switch coupled between the charge pump and a gate of the second DENFET.Type: GrantFiled: April 12, 2019Date of Patent: July 21, 2020Assignee: Cypress Semiconductor CorporationInventors: Nicholas Alexander Bodnaruk, Pradeep Kumar Bajpai, Godwin Gerald Arulappan, Hamid Khodabandehlou
-
Patent number: 10599597Abstract: Techniques for voltage discharge from a USB Power Delivery (USB-PD) VBUS line are described herein. In an example embodiment, an integrated circuit comprises a discharge control logic coupled to a first discharge circuit and to a second discharge circuit. The first discharge circuit configured to couple to a power source node on the VBUS line. The second discharge circuit configured to couple to an output node on the VBUS line. The discharge control logic is configured to independently control the first discharge circuit and the second discharge circuit to discharge the voltage on the VBUS line.Type: GrantFiled: May 18, 2018Date of Patent: March 24, 2020Assignee: Cypress Semiconductor CorporationInventors: Derwin Mattos, Godwin Gerald Arulappan, Syed Raza, Anup Nayak, Sumeet Gupta, Venkat Mandagulathur
-
Publication number: 20190332150Abstract: A semiconductor device for a USB Type-C cable includes a first terminal to couple to a first VCONN line from a first end of the cable, a second terminal to couple to a second VCONN line from the second end of the cable, a charge pump, and a switch circuit coupled to the first terminal and the second terminal. The switch circuit includes a first drain-extended n-type field effect transistor (DENFET) coupled between the first terminal and an internal power supply of the semiconductor device; a first pump switch coupled between the charge pump and a gate of the first DENFET; a second DENFET coupled between the second terminal and the internal power supply; and a second pump switch coupled between the charge pump and a gate of the second DENFET.Type: ApplicationFiled: April 12, 2019Publication date: October 31, 2019Applicant: Cypress Semiconductor CorporationInventors: Nicholas Alexander Bodnaruk, Pradeep Kumar Bajpai, Godwin Gerald Arulappan, Hamid Khodabandehlou
-
Publication number: 20190278731Abstract: Techniques for voltage discharge from a USB Power Delivery (USB-PD) VBUS line are described herein. In an example embodiment, an integrated circuit comprises a discharge control logic coupled to a first discharge circuit and to a second discharge circuit. The first discharge circuit configured to couple to a power source node on the VBUS line. The second discharge circuit configured to couple to an output node on the VBUS line. The discharge control logic is configured to independently control the first discharge circuit and the second discharge circuit to discharge the voltage on the VBUS line.Type: ApplicationFiled: May 18, 2018Publication date: September 12, 2019Applicant: Cypress Semiconductor CorporationInventors: Derwin Mattos, Godwin Gerald Arulappan, Syed Raza, Anup Nayak, Sumeet Gupta, Venkat Mandagulathur
-
Patent number: 10317969Abstract: A semiconductor device for a USB Type-C cable includes a first terminal to couple to a first VCONN line from a first end of the cable, a second terminal to couple to a second VCONN line from the second end of the cable, a charge pump, and a switch circuit coupled to the first terminal and the second terminal. The switch circuit includes a first drain-extended n-type field effect transistor (DENFET) coupled between the first terminal and an internal power supply of the semiconductor device; a first pump switch coupled between the charge pump and a gate of the first DENFET; a second DENFET coupled between the second terminal and the internal power supply; and a second pump switch coupled between the charge pump and a gate of the second DENFET.Type: GrantFiled: September 6, 2018Date of Patent: June 11, 2019Assignee: Cypress Semiconductor CorporationInventors: Nicholas Alexander Bodnaruk, Pradeep Kumar Bajpai, Godwin Gerald Arulappan, Hamid Khodabandehlou
-
Publication number: 20080089321Abstract: A switch circuit, system, and method are provided in which a single, shared data line is formed across the majority of the monolithic substrate which bears the switch. The shared data line is serviced by multiplexers and corresponding state machines placed near the ports of the switch. The state machine determines which one of a plurality of data streams received on the corresponding ports are to be serviced and placed in a first timeslot of multiple timeslots sent across the shared data path. A multiplexer select input responds to the state machine output by forwarding the selected data stream for a duration set by a timer within the state machine. An arbiter within the corresponding state machine determines which port is to served first and which data is to be placed in the first timeslot, but also can prioritize based on user-defined rules.Type: ApplicationFiled: November 30, 2006Publication date: April 17, 2008Applicant: CYPRESS SEMICONDUCTOR CORP.Inventors: Godwin Gerald Arulappan, Vatan Kumar Verma