Abstract: An SRAM cell within a semiconductor device includes p-channel transistors with increased threshold voltages to suppress standby leakage current in the SRAM cell. Existing processing operations already being used to form the semiconductor device, are used to produce the SRAM p-channel devices to have higher threshold voltages than logic p-channel devices also included within the semiconductor device. The processing operations used to form thicker gate oxides for transistors in the I/O portion of the same semiconductor device, may be used to form increased gate oxide thicknesses within the SRAM p-channel transistors. The SRAM p-channel transistors may include a gate oxide that is thicker than the gate oxides of the SRAM n-channel transistors and the logic p-channel transistors. In another embodiment, the gates of the SRAM p-channel transistors may be counterdoped with n-type impurities to produce an effectively greater gate oxide thickness due to poly depletion.

Abstract: A reconfiguration memory device is provided associated with a main memory array. The reconfiguration memory device generates a spare address in real time corresponding to a faulty address. The reconfiguration memory device is coupled to an address line, so that when address information is received for the main memory array, the address information is also received by the reconfiguration memory device. The reconfiguration memory device is adapted to send an output signal that results in the address in the spare memory address array being addressed, if the received address information corresponds to a stored faulty address. The output signal includes a spare control signal that directs components to look to the output of the spare memory.

Abstract: A reconfiguration memory device is provided associated with a main memory array. The reconfiguration memory device generates a spare address in real time corresponding to a faulty address. The reconfiguration memory device is coupled to an address line, so that when address information is received for the main memory array, the address information is also received by the reconfiguration memory device. The reconfiguration memory device is adapted to send an output signal that results in the address in the spare memory address array being addressed, if the received address information corresponds to a stored faulty address. The output signal includes a spare control signal that directs components to look to the output of the spare memory.

Abstract: A computer main memory is divided into multiple physically-separated arrays of memory cells. Each array has associated with it an array of spare memory cells. The array of spare memory cells is located adjacent to its associated main memory cell array. The rows in the spare memory cell array are aligned with the rows in the associated main memory cell array. The main memory blocks are divided into subblocks. Within each subblock, all columns are addressed by a single multiplexer unique to that subblock. A data input bus and a data output bus is provided corresponding to each subblock in the main memory block. Each data input bus and data output bus is electrically coupled to a main memory bus, and each spare memory block. Data can therefore be readily directed either to one of the subblocks in the main memory or to one of the spare memory blocks.

Abstract: A computer main memory is divided into multiple physically-separated arrays of memory cells. Each array has associated with it an array of spare memory cells. The array of spare memory cells is located adjacent to its associated main memory cell array. The rows in the spare memory cell array are aligned with the rows in the associated main memory cell array. The main memory blocks are divided into subblocks. Within each subblock, all columns are addressed by a single multiplexer unique to that subblock. A data input bus and a data output bus is provided corresponding to each subblock in the main memory block. Each data input bus and data output bus is electrically coupled to a main memory bus, and each spare memory block. Data can therefore be readily directed either to one of the subblocks in the main memory or to one of the spare memory blocks.

Abstract: A latching type of sense amplifier, which uses depletion mode transistors as resistive load elements, a pair of enhancement mode field effect transistors as input devices, two other pairs of enhancement mode field effect transistors, and, in addition, a cross-coupled pair of enhancement mode field effect transistors, provides relatively high sensitivity and fast latching time essentially independent of input and output capacitive loading.