Abstract: A signal processor includes a reference clock generator configured to generate a reference clock as a synchronization reference for a signal processing. A counter is configured to count the reference clock. A frequency controller is configured to sample a count value of the counter by utilizing an input clock, to compare an increment value increased from the last sampled value with an expected value, and to control a frequency of the reference clock in accordance with a comparison result.

Abstract: A video signal processor includes a synchronization signal generator configured to generate a first internal synchronization signal corresponding to a standard of an input video signal, and to generate a second internal synchronization signal synchronized with the first internal synchronization signal. A first synchronizer is configured to synchronize the input video signal with the first internal synchronization signal, and to generate a first internal video signal. A second synchronizer is configured to synchronize the first internal video signal with the second internal synchronization signal, and to generate a second internal video signal by controlling the frame rate of the first internal video signal. A codec is configured to execute both decoding of an encoded video signal and encoding of the second internal video signal in designated time partitions within each cycle of the second internal synchronization signal.

Abstract: A video signal processor includes a synchronization signal generator configured to generate a first internal synchronization signal corresponding to a standard of an input video signal, and to generate a second internal synchronization signal synchronized with the first internal synchronization signal. A first synchronizer is configured to synchronize the input video signal with the first internal synchronization signal, and to generate a first internal video signal. A second synchronizer is configured to synchronize the first internal video signal with the second internal synchronization signal, and to generate a second internal video signal by controlling the frame rate of the first internal video signal. A codec is configured to execute both decoding of an encoded video signal and encoding of the second internal video signal in designated time partitions within each cycle of the second internal synchronization signal.

Abstract: A signal processor includes a reference clock generator configured to generate a reference clock as a synchronization reference for a signal processing. A counter is configured to count the reference clock. A frequency controller is configured to sample a count value of the counter by utilizing an input clock, to compare an increment value increased from the last sampled value with an expected value, and to control a frequency of the reference clock in accordance with a comparison result.

Abstract: An image processing apparatus which performs motion compensation prediction image decompression by a small circuit scale. The apparatus comprises: an image memory which is equivalent to a processing region and executes the motion compensation; and an adder. The adder executes interpolation calculation in the event that a reference image is constructed from a motion vector of 1/2 accuracy, and its result therefrom is stored in said image memory. Addition process of the reference image and difference data is processed by the same adder in a time sharing manner.