Abstract: A switching device includes a primary memory and an traffic manager. The primary memory buffers packets for temporary storage. The traffic manager monitors consumed resources in the device related to the buffering of packets in the primary memory. The traffic manager migrates packets buffered in the primary memory to a secondary memory when the consumed resources exceed a certain threshold. The traffic manager also controls dequeuing of the packets from the primary memory and the secondary memory.

Abstract: A service provider or operator of a network often requires the ability to control the amount of data that flows can send and/or receive over a network such that a flow receives at least a predetermined, minimum amount of upstream and/or downstream bandwidth and can potentially utilize excess upstream and/or downstream bandwidth above the minimum amount when available. The present disclosure provides a method and apparatus for implementing a control scheme capable of achieving these and other objectives in a network. In general, the method and apparatus probabilistically meter packets to be sent upstream and/or downstream to determine whether they are in conformance with a service agreement (and at what level of conformance). By using probabilistic metering, smaller width counters can be used to perform the metering over conventional implementations, which reduces power demands and chip space demands.

Abstract: A service provider or operator of a network often requires the ability to control the amount of data that flows can send and/or receive over a network such that a flow receives at least a predetermined, minimum amount of upstream and/or downstream bandwidth and can potentially utilize excess upstream and/or downstream bandwidth above the minimum amount when available. The present disclosure provides a method and apparatus for implementing a control scheme capable of achieving these and other objectives in a network. In general, the method and apparatus probabilistically meter packets to be sent upstream and/or downstream to determine whether they are in conformance with a service agreement (and at what level of conformance). By using probabilistic metering, smaller width counters can be used to perform the metering over conventional implementations, which reduces power demands and chip space demands.

Abstract: A switching device includes a primary memory and an traffic manager. The primary memory buffers packets for temporary storage. The traffic manager monitors consumed resources in the device related to the buffering of packets in the primary memory. The traffic manager migrates packets buffered in the primary memory to a secondary memory when the consumed resources exceed a certain threshold. The traffic manager also controls dequeuing of the packets from the primary memory and the secondary memory.

Abstract: The present disclosure is directed to a system and method for performing out-of-order message filtering with aging. The system and method can be used in a destination device that can receive messages out-of-order (i.e., in a different order than they were transmitted) from a source device. The system and method can filter-out or flag for appropriate handling these messages received out-of-order. To perform the above noted message filtering functionality, the system and method uses a database constructed from a content-addressable memory (CAM) and a random-access memory (RAM) to respectively remember source identifiers and sequence identifiers associated with previously received messages. A source identifier identifies the source of a message, and a sequence identifier identifies the transmission order of the message among the messages transmitted from the particular source. Each message can include a source identifier and a corresponding sequence identifier.

Abstract: A method and apparatus for more efficient routing of packets in a network is provided. The apparatus may include dynamic routing of packets or portions of packets which avoids congestion and blocking by making local decisions within the network. The apparatus may further include creating and updating routing tables which map switch outputs to available network output ports. Additionally the header of packets entering the network are processed prior to entry or as part of the entry to the network to produce a processed packet. The processed packets or portions of packets preferably include complete route information or a final destination address that enables rapid routing through the network without further processing of the packet header. One or more aspects of the inventions may be implemented in combination with other aspects of the invention to further improve network efficiency.

Abstract: A method and apparatus that controls the clock of a digital circuit, and therefore power consumption, without substantially comprising performance is provided. The apparatus may include monitoring the utilization of a First in First Out (FIFO) buffer. For example in a systems and methods according to the invention, clock speed may be reduced when the FIFO is relatively empty and increased when the FIFO is relatively full. The clock speed may be controlled by a phase locked loop, a clock divider, a clock masking device or a combination of more than one of these methods. Power reduction may also be obtained by controlling the clocking of different stages of a pipelined device. One or more aspects of the inventions may be implemented in combination with other aspects of the invention to further reduce power use.

Abstract: The present disclosure is directed to a system and method for performing out-of-order message filtering with aging. The system and method can be used in a destination device that can receive messages out-of-order (i.e., in a different order than they were transmitted) from a source device. The system and method can filter-out or flag for appropriate handling these messages received out-of-order. To perform the above noted message filtering functionality, the system and method uses a database constructed from a content-addressable memory (CAM) and a random-access memory (RAM) to respectively remember source identifiers and sequence identifiers associated with previously received messages. A source identifier identifies the source of a message, and a sequence identifier identifies the transmission order of the message among the messages transmitted from the particular source. Each message can include a source identifier and a corresponding sequence identifier.

Abstract: A method and apparatus for more efficient routing of packets in a network is provided. The apparatus may include dynamic routing of packets or portions of packets which avoids congestion and blocking by making local decisions within the network. The apparatus may further include creating and updating routing tables which map switch outputs to available network output ports. Additionally the header of packets entering the network are processed prior to entry or as part of the entry to the network to produce a processed packet. The processed packets or portions of packets preferably include complete route information or a final destination address that enables rapid routing through the network without further processing of the packet header. One or more aspects of the inventions may be implemented in combination with other aspects of the invention to further improve network efficiency.

Abstract: A method and apparatus for more efficient routing of packets in a network is provided. The apparatus may include dynamic routing of packets or portions of packets which avoids congestion and blocking by making local decisions within the network. The apparatus may further include creating and updating routing tables which map switch outputs to available network output ports. Additionally the header of packets entering the network are processed prior to entry or as part of the entry to the network to produce a processed packet. The processed packets or portions of packets preferably include complete route information or a final destination address that enables rapid routing through the network without further processing of the packet header. One or more aspects of the inventions may be implemented in combination with other aspects of the invention to further improve network efficiency.

Abstract: A method and system can insert multiple packets into a fabric cell. The method or system may be implemented as part of a line card on a switch device. The line card may obtain multiple packets with common packing characteristics, such as destination device, destination port, or priority. The line card may then determine if the multiple packets meet insertion criteria, such as whether the multiple packets together can fit into a fabric cell supported by a switching fabric in the switch device. When the insertion criteria is satisfied, the line card may insert data from the multiple packets into a fabric cell prior to switching the fabric cell through the switching fabric.

Abstract: A method and apparatus that controls the clock of a digital circuit, and therefore power consumption, without substantially comprising performance is provided. The apparatus may include monitoring the utilization of a First in First Out (FIFO) buffer. For example in a systems and methods according to the invention, clock speed may be reduced when the FIFO is relatively empty and increased when the FIFO is relatively full. The clock speed may be controlled by a phase locked loop, a clock divider, a clock masking device or a combination of more than one of these methods. Power reduction may also be obtained by controlling the clocking of different stages of a pipelined device. One or more aspects of the inventions may be implemented in combination with other aspects of the invention to further reduce power use.

Abstract: A method and apparatus that controls the clock of a digital circuit, and therefore power consumption, without substantially comprising performance is provided. The apparatus may include monitoring the utilization of a First in First Out (FIFO) buffer. For example in a systems and methods according to the invention, clock speed may be reduced when the FIFO is relatively empty and increased when the FIFO is relatively full. The clock speed may be controlled by a phase locked loop, a clock divider, a clock masking device or a combination of more than one of these methods. Power reduction may also be obtained by controlling the clocking of different stages of a pipelined device. One or more aspects of the inventions may be implemented in combination with other aspects of the invention to further reduce power use.

Abstract: A method and apparatus for more efficient routing of packets in a network is provided. The apparatus may include dynamic routing of packets or portions of packets which avoids congestion and blocking by making local decisions within the network. The apparatus may further include creating and updating routing tables which map switch outputs to available network output ports. Additionally the header of packets entering the network are processed prior to entry or as part of the entry to the network to produce a processed packet. The processed packets or portions of packets preferably include complete route information or a final destination address that enables rapid routing through the network without further processing of the packet header. One or more aspects of the inventions may be implemented in combination with other aspects of the invention to further improve network efficiency.

Abstract: A method and apparatus that controls the clock of a digital circuit, and therefore power consumption, without substantially comprising performance is provided. The apparatus may include monitoring the utilization of a First in First Out (FIFO) buffer. For example in a systems and methods according to the invention, clock speed may be reduced when the FIFO is relatively empty and increased when the FIFO is relatively full. The clock speed may be controlled by a phase locked loop, a clock divider, a clock masking device or a combination of more than one of these methods. Power reduction may also be obtained by controlling the clocking of different stages of a pipelined device. One or more aspects of the inventions may be implemented in combination with other aspects of the invention to further reduce power use.

Abstract: A method and apparatus that controls the clock of a digital circuit, and therefore power consumption, without substantially comprising performance is provided. The apparatus may include monitoring the utilization of a First in First Out (FIFO) buffer. For example in a systems and methods according to the invention, clock speed may be reduced when the FIFO is relatively empty and increased when the FIFO is relatively full. The clock speed may be controlled by a phase locked loop, a clock divider, a clock masking device or a combination of more than one of these methods. Power reduction may also be obtained by controlling the clocking of different stages of a pipelined device. One or more aspects of the inventions may be implemented in combination with other aspects of the invention to further reduce power use.

Abstract: A novel policer mechanism that incorporates randomization of the rate threshold which prevents “lockup” and “synchronization” problems associated with prior art policers that employ fixed rate thresholds. In one embodiment, a policer machine utilizes the well known sliding window technique to implement traffic control. In a second embodiment, a policer machine utilizes the well known token bucket technique to implement traffic control. In both embodiments, a random dimension is added to the rate threshold used by each policer algorithm. For the sliding window embodiment, the effect of randomization of the rate threshold is that the policer machine applies a scattering of rate values centered around the desired rate to the incoming traffic. For the token bucket embodiment, a random dimension is added to the empty bucket (i.e. zero tokens) threshold.

Abstract: An apparatus for and method of enforcing precedence of committed traffic over excess traffic that overcomes the difficulty in supporting committed over excess traffic and has particular application to distributed queuing systems. Queue control messages are generated and transmitted to other line cards to guarantee that committed traffic is not dropped when sent from multiple sources such as line interface cards to a single destination. When the level of a queue exceeds a threshold and flow control is received for the corresponding destination, the queue starts dropping excess traffic and messages indicating the queue status are sent to all other lines cards. When a line card receives a queue control message that another line card started dropping excess traffic to a specific destination, it also starts dropping excess traffic to that destination as well.

Abstract: An apparatus for and method of enforcing precedence of committed traffic over excess traffic that overcomes the difficulty in supporting committed over excess traffic and has particular application to distributed queuing systems. Queue control messages are generated and transmitted to other line cards to guarantee that committed traffic is not dropped when sent from multiple sources such as line interface cards to a single destination. When the level of a queue exceeds a threshold and flow control is received for the corresponding destination, the queue starts dropping excess traffic and messages indicating the queue status are sent to all other lines cards. When a line card receives a queue control message that another line card started dropping excess traffic to a specific destination, it also starts dropping excess traffic to that destination as well.

Abstract: A forwarding table comprising a combination of a hash table and a content addressable memory (CAM). The forwarding table combines a one way hash table and a small CAM to perform the forwarding information retrieval function. The CAM is used when an address cannot be found in the hash table. When MAC addresses are being added to the forwarding table, they are first tried in the hash table. The address is applied to the hash function and a resulting index input to the hash table. If a hit occurs, it indicates that an entry at that index already exists and a location in the CAM is then allocated for that address. As long as the CAM does not become full, a 100% hit rate is guaranteed. During retrieval, the hash table or the CAM forms the forwarding information output to the next processing stage. If an entry is not found in the hash table, it will typically be found in the CAM. If no entry is found in either, the received frame is flooded to all the ports of the network device.