Abstract: An audio-video platform (AVP) performs as a master controller to interconnect other AV devices and provide unified control of all the AV devices connected to it. The AVP receives all control signals from users and controls slave mode AV devices via an IEEE-1394 bus and master mode AV STBs by using an infrared (IR) blaster, having a command set equivalent to the infrared remote control of the master-mode AV device. The AVP also controls legacy devices via the IR blaster. The AVP has on screen display (OSD) and provides unified graphic user interface (GUI) for connected AV devices. The AVP can transfer compressed AV signals for processing and display in one common format, making it possible to display video from all AV devices.

Abstract: A digital video communication system includes a two-way communication link between a source and a viewer. A video program, in sequential compressed digital form, is repetitively supplied to a fifo memory that has taps corresponding to the number of fixed length segments in the video program. The program is taken from one of the taps and supplied to a one segment-long fifo memory which has taps corresponding to fields in the segment. A program request by a viewer results in the segment at which the beginning of the program will next appear to be addressed and remembered. The field fifo is reset to the first tap and the video program data is processed and transmitted to the viewer from the first field tap. Should the viewer wish to interrupt the video program, a field counter is enabled by an interrupt signal to step over the field taps (at the field rate), thus "freezing" the program. The interrupt signal also causes the address counter to count up (change tap addresses) at the segment rate.

Abstract: A line locked digital color demodulator separates the V and U color components and the burst signal and uses a ROM for providing phase shifts to the V and U demodulation axes. During the burst time of an NTSC signal, the color component axes are shifted by 45.degree. such that the burst signal produces equal components along the axes. A correction signal is developed in response to this shifting and is used in conjunction with a frequency error signal for continuously addressing the ROM. The error signal is developed by counting the number of clock pulses over a 16 line period and comparing the number counted with a standard number for the type signal being received. The error signal is combined with the correction signal for adjusting the phase of the V and U demodulation axes. For a PAL signal, the burst is normalized to always be at 135.degree. and its components along the V and -U axes are compared as with the NTSC signal.

Abstract: A video white compression and peaking arrangement comprises a plurality of inverting amplifier transistors each tied to a common threshold level. RGB input video signals are applied to the inverting amplifier transistors which are ineffective for signals below the threshold level. The transistors are progressively turned on for input signals that exceed the threshold level resulting in non-linear negative feedback signals that compress the output signals by subtraction. A tuned circuit is coupled across the input of each inverting amplifier transistor for bypassing selected frequencies from the negative feedback effect and relatively peaking those frequencies in the output signal.

Abstract: A brightness management arrangement for equalizing the aging of the phosphor screen of a 16:9 aspect ratio cathode ray tube used for 4:3 aspect ratio video displays provides low level illumination of the unused portions of the phosphor screen when displaying 4:3 aspect ratio video. The unused end panels are divided into three sections with the illumination level of each section being determined by the illumination levels of adjacent areas of the 4:3 video display.

Abstract: A television receiver includes conventional systems for receiving a broadcast type signal and displaying the received signal upon a cathode ray tube. Vertical and horizontal scan system oscillators and controls produce vertical and horizontal scan signal synchronized to the reference sync signals. A scan clock system cooperates with the horizontal oscillator and control system to produce horizontal scan related signals which are synchronized to the CRT scan.

Abstract: A television receiver includes a frequency multiplexed video processor which processes chrominance and luminance signals in response to synchronously detected composite video information. The composite video signal is separated into a plurality of frequency spectra which are individually processed utilizing digital electronic circuitry to achieve high performance and cost effectiveness. A comb filter is operative within one of the processors to provide separation of the luminance and chrominance information within the chrominance signal bandpass to maintain high frequency luminance signal components. A separate processor and bandpass filter are operative to provide separate control of the luminance peaking within the system. Conventional luminance and chrominance processing converts the output signals of the multiplexed processor to RGB video signals which are applied to a conventional cathode ray tube display having a conventional deflection system associated therewith.

Abstract: A television receiver includes a frequency multiplexed video processor which processes chrominance and luminance signals in response to synchronously detected composite video information. The composite video signal is separated into a plurality of frequency spectra which are individually processed utilizing digital electronic circuitry to achieve high performance and cost effectiveness. A comb filter is operative within one of the processors to provide separation of the luminance and chrominance information within the chrominance signal bandpass to maintain high frequency luminance signal components. A separate processor and bandpass filter are operative to provide separate control of the luminance peaking within the system. Conventional luminance and chrominance processing converts the output signals of the multiplexed processor to RGB video signals which are applied to a conventional cathode ray tube display having a conventional deflection system associated therewith.

Abstract: A variable speed phase locked loop includes a phase detector and a voltage controlled oscillator, the output of which is provided through a divider circuit to the phase detector. A plurality of delay elements and a decoder divide the period of the phase detector input signal into discrete portions for enabling a plurality of weighted current sources. The current sources are coupled to the phase detector and change its gain. In the locked condition with minimum phase error, the gain of the phase detector is at a minimum and is progressively increased to a maximum when the phase error is maximum.

Abstract: A television receiver includes a frequency multiplexed video processor which processes chrominance and luminance signals in response to synchronously detected composite video information. The composite video signal is separated into a plurality of frequency spectra which are individually processed utilizing digital electronic circuitry to achieve high performance and cost effectiveness. A comb filter is operative within one of the processors to provide separation of the luminance and chrominance information within the chrominance signal bandpass to maintain high frequency luminance signal components. A separate processor and bandpass filter are operative to provide separate control of the luminance peaking within the system. Conventional luminance and chrominance processing converts the output signals of the multiplexed processor to RGB video signals which are applied to a conventional cathode ray tube display having a conventional deflection system associated therewith.

Abstract: A television receiver includes a frequency multiplexed video processor which processes chrominance and luminance signals in response to synchronously detected composite video information. The composite video signal is separated into a plurality of frequency spectra which are individually processed utilizing digital electronic circuitry to achieve high performance and cost effectiveness. A comb filter is operative within one of the processors to provide separation of the luminance and chrominance information within the chrominance signal bandpass to maintain high frequency luminance signal components. A separate processor and bandpass filter are operative to provide separate control of the luminance peaking within the system. Conventional luminance and chrominance processing converts the output signals of the multiplexed processor to RGB video signals which are applied to a conventional cathode ray tube display having a conventional deflection system associated therewith.

Abstract: A television receiver includes a frequency multiplexed video processor which processes chrominance and luminance signals in response to synchronously detected composite video information. The composite video signal is separated into a plurality of frequency spectra which are individually processed utilizing digital electronic circuitry to achieve high performance and cost effectiveness. A comb filter is operative within one of the processors to provide separation of the luminance and chrominance information within the chrominance signal bandpass to maintain high frequency luminance signal components. A separate processor and bandpass filter are operative to provide separate control of the luminance peaking within the system. Separation of chrominance band signals from the luminance signal prior to video clamping provides a burst-free backporch for improved video clamping in a digital video processor.

Abstract: An adaptive oscillator control system for use in television receivers or monitors includes a phase locked loop together with a static phase error correction system which responds to long term error signals of significant magnitude within the phase locked loop to adjust the free-running frequency of the oscillator. An oscillator range control includes a processor having a plurality of established oscillator frequency ranges which are identified by oscillator range code numbers. A measuring counter and clock circuit cooperate to count the number of clock signals occurring during the horizontal sync reference signal period to establish a frequency reference number. A first frequency approximation is provided based upon the oscillator range code number or a known standard scan frequency. A frequency detector examines the oscillator output and provides a second frequency approximation to adjust the oscillator frequency until it falls within the appropriate frequency range.

Abstract: A multiple frequency scan oscillator control system includes a phase locked loop operative upon a scan oscillator to provide phase and frequency synchronization thereof to a periodic reference signal. A static phase error correction is operative to provide adjustment of the free-running or static frequency of the scan oscillator. An error amplifier includes a pair of intercoupled differential amplifier configurations one having a constant current source and the other having a frequency dependent current source which responds to a frequency dependent bias current to alter amplifier gain. A threshold detection circuit includes a differential amplifier pair coupled to a pair of switching circuits for establishing a threshold action in response to system error voltage to indicate large magnitude error voltages and signal the need for free-running frequency adjustment of the oscillator.

Abstract: An adaptive oscillator control system includes a phase locked loop together with a static phase error correction system and external scan system components. An oscillator range control includes a processor having a plurality of established oscillator frequency ranges which are identified by oscillator range code numbers. A first frequency approximation is provided based upon either an oscillator range code number or a known standard scan frequency. A frequency detector provides a second frequency approximation and a confidence circuit examines oscillator consistency and enables the phase locked loop. Thereafter, a lock detector responds to the occurence of frequency and phase lock by the phase lock loop to enable the static phase error corrector and deactivate the oscillator range control system. The lock detector upon detecting horizontal synchronization, for broadcast type video, increases the second frequency approximation range.

Abstract: An adaptive oscillator control system for use in television receivers or monitors includes a phase locked loop together with a static phase error correction system which responds to long term error signals of significant magnitude within the phase locked loop. An oscillator range control includes a processor establishing a plurality of oscillator frequency ranges identified by oscillator range code numbers. First and second frequency approximations are provided using the oscillator range code number. A confidence circuit examines the consistency of oscillator frequency maintenance within the appropriate frequency range and upon establishing the desired confidence level enables the phase locked loop to provide synchronization. Thereafter, a lock detector responds to the occurrence of frequency and phase lock by the phase lock loop to enable the static phase error corrector and deactivate the oscillator range control system.

Abstract: A static phase error responsive oscillator control includes a phase detector coupled to a source of horizontal synchronizing pulses, a low pass filter, an error amplifier, a voltage controlled oscillator having a frequency equal to a multiple of the horizontal scan frequency, and a corresponding frequency divider. A threshold detector responds to error signals in excess of predetermined upper and lower thresholds to indicate large magnitude frequency corrections. An averaging circuit determines the long term character of the large magnitude corrections to alter the free-running or static frequency of the oscillator. Once the free-running frequency is corrected, static phase error is substantially reduced or eliminated.

Abstract: A method and apparatus for separating sync pulses by charging a capacitor to the sync tip voltage level during occurrence of a sync pulse and discharging the capacitor to the back porch voltage level for an equal duration. The discharge duration is determined by decrementing an up/down counter that was incremented during the sync pulse. A comparator separates the sync pulses by comparing the composite video signal with the voltage on the capacitor.

Abstract: A horizontal phase locked loop includes a horizontal phase detector having a current source transistor with a pair of resistors connected across its base-emitter circuit. A switching transistor, supplied with an input signal during the vertical blanking interval, is coupled across one of the resistors for shorting out that resistor during the non-vertical blanking interval. The current from the source transistor is increased during the vertical blanking interval which increases the gain of the phase locked loop and eliminates the hook at the top of the raster when a video signal with phase errors during vertical is received.

Abstract: A color signal correction circuit matrixes the R-Y and B-Y color difference signals to develop an I axis signal for application to a signal correction circuit. The I axis signal is also supplied to a comparator which feeds a counter, the output of which is connected to a digital-to-analog converter that, in turn, supplies the comparator and the color signal correction circuit. The comparator and the counter are enabled during the color burst time when there is no color in the color difference signals. The DC level of the I matrix is determined by the count in the counter to enable the color signal correction circuit to determine the polarity and magnitude of the I axis signal and provide appropriate correction to the B-Y color difference signal.