Abstract: Apparatuses, systems, and techniques to process image data. In at least one embodiment, a neural network is trained to perform demosacing of two-dimensional image data obtained from an image sensor.

Abstract: An integrated digital BTSC encoder with an improved pilot signal generator substantially implemented on a single CMOS integrated circuit. By digitally generating a sinusoid that is frequency locked to a two-state input reference signal using a high rate internal clock, a hardware-efficient BTSC pilot signal generator is provided with good acquisition and tracking performance. Implemented efficiently as a simple phase detector, a low-complexity loop filter, a pilot frequency offset adder, a phase accumulator and a sinusoidal generator, the invention enables lower-rate post-processing of the pilot tone without a costly variable interpolator decimator structures.

Abstract: All digital reference frequency locking. An all digital approach is provided for operation within one or more CMs within a cable modem communication system to lock the upstream of the one or more CMs to the downstream symbol clock provided from a CMTS. The locking of the CM's upstream may be performed using one of at least three different functions: (1) Locking the upstream symbol clock phase to the downstream symbol clock phase, (2) Locking the downstream symbol clock phase to the headend reference clock phase (typically 10.24 MHz or integer multiple thereof), and (3) Locking the upstream carrier frequency to the downstream symbol clock frequency. The all-digital techniques for supporting all digital reference frequency locking functionality provide high performance to support S-CDMA and other synchronous modulation techniques.

Abstract: A spatial diversity combiner comprises a plurality of feed forward equalizers (FFEs), a decision feedback equalizer (DFE), and a tap control circuit. The plurality of FFEs receive spatially diverse replicas of an RF signal and optimally combine them. The DFE provides feedback for tap weight control and optimal equalization of the transmission channel. Symbol error is generated by a slicer circuit or by a maximum likelihood sequence estimation (MLSE) process.