Abstract: Where links between a port module and plural switch fabric slices are of various lengths, a cell is transmitted from the port module to a switch fabric slice in response to a grant. The transmission is delayed by an amount based on a link round trip delay (RTD) value for the corresponding link between the port module and the switch fabric slice, and a predetermined global delay value. As a result of this delay, the cell arrives at the switch fabric slice at a fixed number of cell times (equal to the global delay value) after issuance of the grant, independent of any link lengths.

Abstract: A switching fabric connects input ports to output ports. Each input has an input pointer referencing an output port, and each output has an output pointer referencing an input port. An arbiter includes input and output credit allocators, and an arbitration module (matcher). The input credit allocator resets input credits associated with input/output pairs and updates the input pointers. Similarly, the output credit allocator resets output credits associated with input/output pairs and updates the output pointers. The matcher matches inputs to outputs based on pending requests and available input and output credits. A scheduler schedules transmissions through the cross-bar switch according to the arbiter's matches.

Abstract: Data cells of plural classes are transferred from input ports to output ports through a switch by storing the cells at each input port in class-specific virtual output queues (VOQ) within sets of VOQs associated with output ports, and providing credits to VOQs according to class-associated guaranteed bandwidths. When a cell is received at a VOQ having credits, a high-priority request for transfer is generated. If a cell is received at a VOQ that does not have any available credits, a low-priority request for transfer is generated. In response to requests, grants are issued to VOQ sets without regard to class, high-priority requests being favored over low-priority requests. When a grant is received for a particular VOQ set, an arbitrator selects a VOQ from the set, giving priority to VOQs having credits over VOQs without credits, and a cell from the selected VOQ is transferred.

Abstract: Where links between a port module and plural switch fabric slices are of various lengths, a cell is transmitted from the port module to a switch fabric slice in response to a grant. The transmission is delayed by an amount based on a link round trip delay (RTD) value for the corresponding link between the port module and the switch fabric slice, and a predetermined global delay value. As a result of this delay, the cell arrives at the switch fabric slice at a fixed number of cell times (equal to the global delay value) after issuance of the grant, independent of any link lengths.

Abstract: A switching fabric connects input ports to output ports. Each input has an input pointer referencing an output port, and each output has an output pointer referencing an input port. An arbiter includes input and output credit allocators, and an arbitration module (matcher). The input credit allocator resets input credits associated with input/output pairs and updates the input pointers. Similarly, the output credit allocator resets output credits associated with input/output pairs and updates the output pointers. The matcher matches inputs to outputs based on pending requests and available input and output credits. A scheduler schedules transmissions through the cross-bar switch according to the arbiter's matches.

Abstract: Data cells of plural classes are transferred from input ports to output ports through a switch by storing the cells at each input port in class-specific virtual output queues (VOQ) within sets of VOQs associated with output ports, and providing credits to VOQs according to class-associated guaranteed bandwidths. When a cell is received at a VOQ having credits, a high-priority request for transfer is generated. If a cell is received at a VOQ that does not have any available credits, a low-priority request for transfer is generated. In response to requests, grants are issued to VOQ sets without regard to class, high-priority requests being favored over low-priority requests. When a grant is received for a particular VOQ set, an arbitrator selects a VOQ from the set, giving priority to VOQs having credits over VOQs without credits, and a cell from the selected VOQ is transferred.

Abstract: A novel protocol for scheduling of packets in high-speed cell based switches is provided. The switch is assumed to use a logical cross-bar fabric with input buffers. The scheduler may be used in optical as well as electronic switches with terabit capacity. The proposed round-robin greedy scheduling (RRGS) achieves optimal scheduling at terabit throughput, using a pipeline technique. The pipeline approach avoids the need for internal speedup of the switching fabric to achieve high utilization.

Abstract: An overlay model to let multiple VPNs share the same physical switches while maintaining their individual resource and administrative boundaries. A clean resource and protocol management structure within the ATM switches is provided for the overlay model. An architectural framework for such resource and protocol management within multiprocessor ATM switches is provided. Multiple protocols are supported both at the switch level and at the port level. A VPN on a switch can be configured with any of the existing control protocols available on that switch. This protocol management mechanism is then extended for providing intra-VPN multiprotocol support where a single VPN is allowed to use multiple control protocols on the same switch port. A mechanism for Network Management System (NMS) coordinated VPN creation and configuration is provided.

Abstract: A buffer management scheme for an ATM switch where the static and dynamic thresholds are applied appropriately at different levels to ensure efficient and fair usage of buffer memory. A novel dynamic threshold mechanism which, while ensuring fair sharing of memory, maximizes the overall memory utilization.

Abstract: A Dynamic Rate Control (DRC) scheduler for scheduling cells for service in a generic Asynchronous Transfer Mode (ATM) switch is disclosed. According to the inventive DRC, each traffic stream associated with an internal switch queue is rate-shaped according to a rate which consists of a minimum guaranteed rate and a dynamic component computed based on congestion information within the switch. While achieving high utilization, DRC guarantees a minimum throughput for each stream and fairly distributes unused bandwidth. The distribution of unused bandwidth in DRC can be assigned flexibly, i.e., the unused bandwidth need not be shared in proportion to the minimum throughput guarantees, as in weighted fair share schedulers. Moreover, an effective closed-loop QoS control can be built into DRC by dynamically updating a set of weights based on observed QoS. Another salient feature of DRC is its ability to control congestion internal congestion at bottleneck points within a multistage switch.

Abstract: A large capacity ATM core switch architecture is disclosed, which supports multiple traffic classes and quality-of-service (QoS) guarantees. The switch supports both real-time traffic classes with strict QoS requirements, e.g., CBR and VBR, and non-real-time traffic classes with less stringent requirements, e.g., ABR and UBR. The architecture also accommodates real-time and non-real-time multicast flows in an efficient manner. The switch consists of a high-speed core module that interconnects input/output modules with large buffers and intelligent scheduling/buffer management mechanisms. The scheduling can be implemented using a novel dynamic rate control, which controls internal congestion and achieves fair throughput performance among competing flows at switch bottlenecks. In the dynamic rate control scheme, flows are rate-controlled according to congestion information observed at bottleneck points within the switch.

Abstract: A scheme for determining the usage parameter control (UPC) values for an arbitrary traffic source from observations of its emitted cell stream is disclosed. The UPC values are used in a traffic shaping mechanism based on a dual leaky bucket, which shapes the cell stream by either discarding or delaying cells. The choice of UPC values is a function of the statistical characteristics of the observed cell stream; the user's tolerance for delay prior to the network access point; and the cost incurred on the network side. The chosen UPC values are then negotiated with the network. The source traffic characteristics may change dramatically over time, making the initially negotiated UPC descriptor inappropriate for the entire traffic stream. Hence, a method is disclosed for dynamically renegotiating UPC parameters whenever a predetermined change in traffic characteristics is detected.

Abstract: The present invention pertains to message sets for use in a flexible programmable multiplexer for accessing an Asynchronous Transfer Mode (ATM) network. The access multiplexer uses a functional separation of line related functions and protocol related functions. Line interface cards perform line related functions. A message set for use in such a multiplexing system that uses a functional separation of line and protocol related functions is provided. The message set includes a general message, a hello message, a configuration message, a line stabilized message, an identify remote message, an identify remote acknowledgement message, a reset remote message, a report statistics message, a report statistics acknowledgement message, a loopback test message and a dynamic rate adaptation message. A flexible programmable multiplexer that uses the message set is also provided.

Abstract: A multi-class connection admission control (CAC) method that supports cell loss and delay requirements. In this model-based CAC, the source traffic is described in terms of the usage parameter control (UPC) parameters. Through analysis and approximations, simple closed-form methods to calculate the bandwidth required to meet guarantees on quality of service (QoS) are used. In addition to being robust, the CAC achieves a high level of resource utilization and can be easily implemented for real-time admission control.

Abstract: A rate based feedback congestion control at an ATM switch for ABR vservice is based upon the state of the switch queue fill. Individual ABR virtual channels are informed of an explicit rate at which the virtual channels are allowed to transmit cells.

Abstract: A system for variable bit-rate video coding in which encoding bandwidth as characterized by a usage parameter control (UPC) parameters is renegotiated between a video encoder and an asynchronous transfer mode network in order to maintain quality-of-service and save bandwidth. The coding system includes adjusting the video source quantization in a manner for controlling the occupancy level of a buffer while new UPC parameters are requested from an ATM network.

Abstract: An asynchronous transfer mode (ATM) traffic control framework is based on an integrated usage parameter control (UPC) approach, which approach provides a unified and scalable solution to the issue of quality-of-services (QOS) levels over a range of anticipated services in ATM based networks. The approach is consistent with emerging ATM Forum and CCITT standards. Additionally, a UPC-based call and burst admission control providing the desired QOS over periods of network overload by call/burst admission control and traffic shaping of source stream preferably uses a dual leaky bucket.

Abstract: A control method and architecture is described for an ATM network carrying connectionless data traffic. The method is capable of integrating connection-oriented as well as connectionless traffic. The method takes advantage of the quasi-deterministic nature of the traffic emanating from a source that is being shaped by the leaky bucket shaping algorithm. Alternative methods are provided if such a shaping algorithm is not provided by the CPE which methods still guarantee performance that equals or exceeds shared media networks such as FDDI. Hardware and software embodiments of the methods are disclosed. The invention is particularly applicable to LANs and hubs.

Abstract: To control congestion in packet switching networks, control of the traffic sent by a given station to each of the downstream nodes to which it is directly connected is effected by control of the traffic that the upstream nodes to which it is directly connected are permitted to send to it. In this regard, a predictive model is used to predict the cross traffic, one round trip delay in advance that the given station can expect. The parameters for the predictive model are obtained by measurements in real time and by the use of moving averages. Using the predicted cross traffic, the amount of controlled traffic that the proximate downstream nodes can accommodate from the given node, and the correct state of the given node, the state of the given node one round trip delay into the future is predicted. This prediction is used to schedule the amount of traffic to be sent by each of its proximate upstream nodes.