Abstract: Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

Abstract: Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits. The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

Abstract: Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits. The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

Abstract: Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits. The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

Abstract: Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

Abstract: Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

Abstract: Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

Abstract: Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits. The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

Abstract: Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits. The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

Abstract: Methods and apparatus for multi-threading on a simultaneous multi-threading processor are provided. The methods and apparatus described herein increase computational throughput by launching two or more computational threads to perform the same algorithm using two different software segments. One of the software segments is coded to perform the algorithm using primarily a first processor resource (e.g., a floating point unit). Another software segment is coded to perform the same algorithm using a primarily a second processor resource (e.g., an integer execution unit). A workload requiring execution of the algorithm is allocated to the threads in a balanced manner (e.g., faster code segments are given more of the workload). The threads use different processor resources, therefore the threads are able to execute in parallel in an efficient manner. When each of the threads completes execution, the results may be synchronized.

Abstract: A method and system to identify serial code regions in applications is described. The method includes instrumenting an application's code at loop entry points and loop exit points and gathering data about a plurality of loops in the application. The data may include the amount of time spent in each loop, the number of times each loop is executed, and/or loop hierarchies. A list of the loops may be displayed based on the gathered data. One or more of the plurality of loops may be selected for threading based on the gathered data. Directives may then be inserted into the application's code to thread one or more of the plurality of loops. The threaded loops may then be simulated and any resulting errors may be displayed.

Abstract: A rendering cost estimation method is provided for generating a rendering cost estimate that that is sufficiently close to an actual rendering cost that would be incurred if computer-generated images were actually rendered from a computer-graphics model. A plurality of cost factors that affect the actual rendering cost are identified. Representative information, including rendering cost estimation parameters that adequately characterize the cost factors, is derived from the computer-graphics model. The estimation parameters are combined with rendering cost estimation relationships that express the affect of the cost factors on the rendering cost. A rendering cost estimate is generated based on the estimation parameters derived from the computer-graphics model and the estimation relationships.

Abstract: Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits. The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

Abstract: Methods and apparatus for multi-threading on a simultaneous multi-threading processor are provided. The methods and apparatus described herein increase computational throughput by launching two or more computational threads to perform the same algorithm using two different software segments. One of the software segments is coded to perform the algorithm using primarily a first processor resource (e.g., a floating point unit). Another software segment is coded to perform the same algorithm using a primarily a second processor resource (e.g., an integer execution unit). A workload requiring execution of the algorithm is allocated to the threads in a balanced manner (e.g., faster code segments are given more of the workload). The threads use different processor resources, therefore the threads are able to execute in parallel in an efficient manner. When each of the threads completes execution, the results may be synchronized.

Abstract: A rendering cost estimation method is provided for generating a rendering cost estimate that that is sufficiently close to an actual rendering cost that would be incurred if computer-generated images were actually rendered from a computer-graphics model. A plurality of cost factors that affect the actual rendering cost are identified. Representative information, including rendering cost estimation parameters that adequately characterize the cost factors, is derived from the computer-graphics model. The estimation parameters are combined with rendering cost estimation relationships that express the affect of the cost factors on the rendering cost. A rendering cost estimate is generated based on the estimation parameters derived from the computer-graphics model and the estimation relationships.

Abstract: A rendering cost estimation method is provided for generating a rendering cost estimate that that is sufficiently close to an actual rendering cost that would be incurred if computer-generated images were actually rendered from a computer-graphics model. A plurality of cost factors that affect the actual rendering cost are identified. Representative information, including rendering cost estimation parameters that adequately characterize the cost factors, is derived from the computer-graphics model. The estimation parameters are combined with rendering cost estimation relationships that express the affect of the cost factors on the rendering cost. A rendering cost estimate is generated based on the estimation parameters derived from the computer-graphics model and the estimation relationships.

Abstract: The present invention converts an unstructured grid of finite volume data to a rectangular grid of voxel definitions for use by a volume rendering technique operable on such a rectangular grid of voxel definitions. The unstructured finite element grid is sliced using a slicing process generating intersection polygons at scalar data at polygon vertices. This vertex scalar data is then mapped to shades of a color based on a linear mapping function. A linear interpolation is then utilized to generate a rectangular two dimensional array, for each slicing interval, which is dependent upon a pixel resolution of the display device utilized within the data processing system implementing the present invention. Each pixel represents a three-dimensional point in the viewing coordinate space wherein each pixel represents a voxel corner. The color of each pixel is used to determine the scalar value to be associated with each voxel corner.

Abstract: A 3D scientific visualization system for viewing models composed of polyhedra or other elements having vertices at which analysis results (e.g., temperature or pressure) are defined. The model is viewed either in a cutting plane or as a contour surface in which a given result assumes a specified value. Polygons making up an intersection surface formed by the intersection of the cutting plane or contour surface with the polyhedra forming the model are generated and passed to a polygon processor for rendering and display on a raster-scan device. A series of intersection surfaces are generated for display by varying either the position of the cutting plane along its normal or the value that the result assumes on the contour surface.