Abstract: Techniques for use in integrated circuit design systems for reducing metal fill insertion time in the integrated circuit design process. In one example, a method includes the following steps. Metal fill data associated with a given layout from a placement and routing database of an integrated circuit design system is stored. The metal fill data is purged from the placement and routing database. At least one change to layout data in the placement and routing database is implemented. The stored metal fill data is loaded into the placement and routing database after the at least one change is implemented to the layout data. A check is performed for an existence of one or more violations associated with the metal fill data due to implementing the at least one change to the layout data in the placement and routing database. A correction procedure is performed on the metal fill data when one or more violations exist.

Abstract: Techniques for use in integrated circuit design systems for reducing metal fill insertion time in the integrated circuit design process. In one example, a method includes the following steps. Metal fill data associated with a given layout from a placement and routing database of an integrated circuit design system is stored. The metal fill data is purged from the placement and routing database. At least one change to layout data in the placement and routing database is implemented. The stored metal fill data is loaded into the placement and routing database after the at least one change is implemented to the layout data. A check is performed for an existence of one or more violations associated with the metal fill data due to implementing the at least one change to the layout data in the placement and routing database. A correction procedure is performed on the metal fill data when one or more violations exist.

Abstract: Reducing timing skew begins with identifying signals that are to have a reduced timing skew. These identified signals are then routed to reduce the layout distance of each signal path. Among these identified signals, a longest signal path is found and the signal paths of the remaining identified signals are lengthened. The lengthening is done to each of the remaining identified signal paths to each have a length substantially equal to the longest signal path whereby the timing skew between the identified signals is reduced. A signal length matching process may be stored as a program in a computer-readable medium with the program operable on a computer system tailored for providing chip placement and routing processes.

Abstract: Reducing timing skew begins with identifying signals that are to have a reduced timing skew. These identified signals are then routed to reduce the layout distance of each signal path. Among these identified signals, a longest signal path is found and the signal paths of the remaining identified signals are lengthened. The lengthening is done to each of the remaining identified signal paths to each have a length substantially equal to the longest signal path whereby the timing skew between the identified signals is reduced. A signal length matching process may be stored as a program in a computer-readable medium with the program operable on a computer system tailored for providing chip placement and routing processes.