Patents by Inventor Gordon Caruk
Gordon Caruk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230342325Abstract: A link controller includes a Peripheral Component Interconnect Express (PCIe) physical layer circuit for coupling to a communication link and providing a data path over the communication link, a first data link layer controller which operates according to a PCIe protocol, and a second data link layer controller which operates according to a non-PCIe protocol. A multiplexer-demultiplexer selectively connects both data link layer controllers to the PCIe physical layer circuit. A protocol translation circuit is coupled between the multiplexer-demultiplexer and the second data link layer controller, the protocol translation circuit receiving traffic data from the second data link layer controller in a non-PCIe format, encapsulating the non-PCIe format in a PCIe format, and passing traffic data to the multiplexer-demultiplexer circuit.Type: ApplicationFiled: June 30, 2023Publication date: October 26, 2023Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Gordon Caruk, Maurice B. Steinman, Gerald R. Talbot, Joseph D. Macri
-
Patent number: 11693813Abstract: A link controller includes a Peripheral Component Interconnect Express (PCIe) physical layer circuit for coupling to a communication link and providing a data path over the communication link, a first data link layer controller which operates according to a PCIe protocol, and a second data link layer controller which operates according to a Gen-Z protocol. A multiplexer-demultiplexer selectively connects both data link layer controllers to the PCIe physical layer circuit. A protocol translation circuit is coupled between the multiplexer-demultiplexer and the second data link layer controller, the protocol translation circuit receiving traffic data from the second data link layer controller in a Gen-Z format, encapsulating the Gen-Z format in a PCIe format, and passing traffic data to the multiplexer-demultiplexer circuit.Type: GrantFiled: May 30, 2019Date of Patent: July 4, 2023Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Gordon Caruk, Maurice B. Steinman, Gerald R. Talbot, Joseph D. Macri
-
Patent number: 11301410Abstract: An electronic device includes a requester and a link interface coupled between the requester and a link. The requester is configured to send a request packet to a completer on the link via the link interface. When sending the request packet to the completer, the requester sends, to the completer via the link interface, the request packet with a tag that is not unique with respect to tags in other request packets from the requester that will be in the internal elements of the completer before the request packet is in the internal elements of the completer, but that is unique with respect to tags in other request packets from the requester that will be in the internal elements of the completer while the request packet is in the internal elements of the completer.Type: GrantFiled: December 13, 2020Date of Patent: April 12, 2022Assignee: ADVANCED MCIRO DEVICES, INC.Inventor: Gordon Caruk
-
Publication number: 20220035765Abstract: An interconnect controller for a data processing platform includes a data link layer controller for selectively receiving data packets from and sending data packets to a higher protocol layer, and a physical layer controller coupled to the data link layer controller and adapted to be coupled to a communication link. The physical layer controller operates according to a predetermined protocol selectively at one of a plurality of enhanced speeds that are not specified by any published standard and are separated from each other by the same predetermined amount. In response to performing a link initialization, the interconnect controller performs at least one setup operation to select a speed, and subsequently operates the communication link using a selected speed.Type: ApplicationFiled: October 18, 2021Publication date: February 3, 2022Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Gordon Caruk, Gerald R. Talbot
-
Patent number: 11151075Abstract: An interconnect controller includes a data link layer controller coupled to a transaction layer, wherein the data link layer controller selectively receives data packets from and sends data packets to the transaction layer, and a physical layer controller coupled to the data link layer controller and to a communication link. The physical layer controller selectively operates at a first predetermined link speed. The physical layer controller has an enhanced speed mode, wherein in response to performing a link initialization, the interconnect controller queries a data processing platform to determine whether the enhanced speed mode is permitted, performs at least one setup operation to select an enhanced speed, wherein the enhanced speed is greater than the first predetermined link speed, and subsequently operates the communication link using the enhanced speed.Type: GrantFiled: December 14, 2018Date of Patent: October 19, 2021Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Gordon Caruk, Gerald R. Talbot
-
Patent number: 11055242Abstract: Methods and devices for handling short Peripheral Component Interconnect Express (PCIe) Transaction Layer Packets (TLPs) are described. A receiver can receive at least a portion of a first packet and can process the first packet to determine if the first packet is a short packet. The receiver can receive at least a portion of a second packet and if the first packet is a short packet, the receiver can transmit a negative acknowledgement (NAK) in response to the second packet and can receive a retransmission of the second packet.Type: GrantFiled: June 24, 2016Date of Patent: July 6, 2021Assignee: ATI Technologies ULCInventors: Gordon Caruk, Jaroslaw Marczewski
-
Patent number: 10936530Abstract: A method and apparatus for determining link bifurcation availability implemented in a computer system includes assigning, by a controller, lanes that include links for one or more components connected in accordance with a current known configuration. The controller transmits ordered sets including the assignments to the one or more components which are received by the one or more components. The one or more components respond with a first link to the controller. Based upon the links received by the controller not meeting the current known configuration, the controller issues an interrupt and is reconfigured.Type: GrantFiled: July 24, 2019Date of Patent: March 2, 2021Assignee: ATI TECHNOLOGIES ULCInventors: Natale Barbiero, Gordon Caruk
-
Publication number: 20210026797Abstract: A method and apparatus for determining link bifurcation availability implemented in a computer system includes assigning, by a controller, lanes that include links for one or more components connected in accordance with a current known configuration. The controller transmits ordered sets including the assignments to the one or more components which are received by the one or more components. The one or more components respond with a first link to the controller. Based upon the links received by the controller not meeting the current known configuration, the controller issues an interrupt and is reconfigured.Type: ApplicationFiled: July 24, 2019Publication date: January 28, 2021Applicant: ATI Technologies ULCInventors: Natale Barbiero, Gordon Caruk
-
Patent number: 10698856Abstract: A link controller, method, and data processing platform are provided with dual-protocol capability. The link controller includes a physical layer circuit for providing a data lane over a communication link, a first data link layer controller which operates according to a first protocol, and a second data link layer controller which operates according to a second protocol. A multiplexer/demultiplexer selectively connects both data link layer controllers to the physical layer circuit. A link training and status state machine (LTSSM) selectively controls the physical layer circuit to transmit and receive first training ordered sets over the data lane, and inside the training ordered sets, transmit and receive alternative protocol negotiation information over the data lane. In response to receiving the alternative protocol negotiation information, the LTSSM causes the multiplexer/demultiplexer to selectively connect the physical layer circuit to the second data link layer controller.Type: GrantFiled: December 18, 2018Date of Patent: June 30, 2020Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Gordon Caruk, Gerald R. Talbot
-
Publication number: 20200192850Abstract: A link controller, method, and data processing platform are provided with dual-protocol capability. The link controller includes a physical layer circuit for providing a data lane over a communication link, a first data link layer controller which operates according to a first protocol, and a second data link layer controller which operates according to a second protocol. A multiplexer/demultiplexer selectively connects both data link layer controllers to the physical layer circuit. A link training and status state machine (LTSSM) selectively controls the physical layer circuit to transmit and receive first training ordered sets over the data lane, and inside the training ordered sets, transmit and receive alternative protocol negotiation information over the data lane. In response to receiving the alternative protocol negotiation information, the LTSSM causes the multiplexer/demultiplexer to selectively connect the physical layer circuit to the second data link layer controller.Type: ApplicationFiled: December 18, 2018Publication date: June 18, 2020Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Gordon Caruk, Gerald R. Talbot
-
Publication number: 20200192853Abstract: A link controller includes a Peripheral Component Interconnect Express (PCIe) physical layer circuit for coupling to a communication link and providing a data path over the communication link, a first data link layer controller which operates according to a PCIe protocol, and a second data link layer controller which operates according to a Gen-Z protocol. A multiplexer-demultiplexer selectively connects both data link layer controllers to the PCIe physical layer circuit. A protocol translation circuit is coupled between the multiplexer-demultiplexer and the second data link layer controller, the protocol translation circuit receiving traffic data from the second data link layer controller in a Gen-Z format, encapsulating the Gen-Z format in a PCIe format, and passing traffic data to the multiplexer-demultiplexer circuit.Type: ApplicationFiled: May 30, 2019Publication date: June 18, 2020Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Gordon Caruk, Maurice B. Steinman, Gerald R. Talbot, Joseph D. Macri
-
Publication number: 20200192852Abstract: An interconnect controller includes a data link layer controller coupled to a transaction layer, wherein the data link layer controller selectively receives data packets from and sends data packets to the transaction layer, and a physical layer controller coupled to the data link layer controller and to a communication link. The physical layer controller selectively operates at a first predetermined link speed. The physical layer controller has an enhanced speed mode, wherein in response to performing a link initialization, the interconnect controller queries a data processing platform to determine whether the enhanced speed mode is permitted, performs at least one setup operation to select an enhanced speed, wherein the enhanced speed is greater than the first predetermined link speed, and subsequently operates the communication link using the enhanced speed.Type: ApplicationFiled: December 14, 2018Publication date: June 18, 2020Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Gordon Caruk, Gerald R. Talbot
-
Publication number: 20190012760Abstract: Methods and apparatus for providing multiple graphics processing capacity, while utilizing unused integrated graphics processing circuitry on a bridge circuit along with an external or discrete graphics processing unit is disclosed. In particular, a bridge circuit includes an integrated graphics processing circuit configured to process graphics jobs. The bridge circuit also includes an interface operable according to interface with a discrete graphics processing circuit. A controller is included with the bridge circuit and responsive whenever the discrete graphics processing circuit is coupled to the interface to cause the integrated graphics processing circuit to process a task of the graphics job in conjunction with operation of the discrete graphics processing circuit that is operable to process another task of the graphics job. Corresponding methods are also disclosed.Type: ApplicationFiled: January 8, 2018Publication date: January 10, 2019Inventors: Grigori Temkine, Gordon Caruk, Oleg Drapkin
-
Patent number: 9865030Abstract: Methods and apparatus for providing multiple graphics processing capacity, while utilizing unused integrated graphics processing circuitry on a bridge circuit along with an external or discrete graphics processing unit is disclosed. In particular, a bridge circuit includes an integrated graphics processing circuit configured to process graphics jobs. The bridge circuit also includes an interface operable according to interface with a discrete graphics processing circuit. A controller is included with the bridge circuit and responsive whenever the discrete graphics processing circuit is coupled to the interface to cause the integrated graphics processing circuit to process a task of the graphics job in conjunction with operation of the discrete graphics processing circuit that is operable to process another task of the graphics job. Corresponding methods are also disclosed.Type: GrantFiled: August 5, 2016Date of Patent: January 9, 2018Assignee: ATI Technologies ULCInventors: Grigori Temkine, Gordon Caruk, Oleg Drapkin
-
Publication number: 20160378702Abstract: Methods and devices for handling short Peripheral Component Interconnect Express (PCIe) Transaction Layer Packets (TLPs) are described. A receiver can receive at least a portion of a first packet and can process the first packet to determine if the first packet is a short packet. The receiver can receive at least a portion of a second packet and if the first packet is a short packet, the receiver can transmit a negative acknowledgement (NAK) in response to the second packet and can receive a retransmission of the second packet.Type: ApplicationFiled: June 24, 2016Publication date: December 29, 2016Applicant: ATI Technologies ULCInventors: Gordon Caruk, Jaroslaw Marczewski
-
Publication number: 20160364834Abstract: Methods and apparatus for providing multiple graphics processing capacity, while utilizing unused integrated graphics processing circuitry on a bridge circuit along with an external or discrete graphics processing unit is disclosed. In particular, a bridge circuit includes an integrated graphics processing circuit configured to process graphics jobs. The bridge circuit also includes an interface operable according to interface with a discrete graphics processing circuit. A controller is included with the bridge circuit and responsive whenever the discrete graphics processing circuit is coupled to the interface to cause the integrated graphics processing circuit to process a task of the graphics job in conjunction with operation of the discrete graphics processing circuit that is operable to process another task of the graphics job. Corresponding methods are also disclosed.Type: ApplicationFiled: August 5, 2016Publication date: December 15, 2016Inventors: Grigori Temkine, Gordon Caruk, Oleg Drapkin
-
Patent number: 9424622Abstract: Methods and apparatus for providing multiple graphics processing capacity, while utilizing unused integrated graphics processing circuitry on a bridge circuit along with an external or discrete graphics processing unit is disclosed. In particular, a bridge circuit includes an integrated graphics processing circuit configured to process graphics jobs. The bridge circuit also includes an interface operable according to interface with a discrete graphics processing circuit. A controller is included with the bridge circuit and responsive whenever the discrete graphics processing circuit is coupled to the interface to cause the integrated graphics processing circuit to process a task of the graphics job in conjunction with operation of the discrete graphics processing circuit that is operable to process another task of the graphics job. Corresponding methods are also disclosed.Type: GrantFiled: June 24, 2013Date of Patent: August 23, 2016Assignee: ATI Technologies ULCInventors: Grigori Temkine, Gordon Caruk, Oleg Drapkin
-
Patent number: 9244872Abstract: A communications controller includes a physical interface and an internal transmit and receive circuit. The physical interface has a port for connection to a communication medium, an input, and an output, and operates to receive a first sequence of data bits from the input and to transmit the first sequence of data bits to the port, and to receive a second sequence of data bits from the port and to conduct said second sequence of data bits to the output. The internal transmit and receive circuit is coupled to the physical interface, and has an internal architecture to conduct a first plurality of symbols at a first rate in a low frequency mode and a second plurality of symbols at a second rate in a low latency mode, wherein the first plurality is greater in number than the second plurality, and the second rate is higher than the first rate.Type: GrantFiled: December 21, 2012Date of Patent: January 26, 2016Assignee: ATI TECHNOLOGIES ULCInventors: Natale Barbiero, Gordon Caruk
-
Publication number: 20140181355Abstract: A communications controller includes a physical interface and an internal transmit and receive circuit. The physical interface has a port for connection to a communication medium, an input, and an output, and operates to receive a first sequence of data bits from the input and to transmit the first sequence of data bits to the port, and to receive a second sequence of data bits from the port and to conduct said second sequence of data bits to the output. The internal transmit and receive circuit is coupled to the physical interface, and has an internal architecture to conduct a first plurality of symbols at a first rate in a low frequency mode and a second plurality of symbols at a second rate in a low latency mode, wherein the first plurality is greater in number than the second plurality, and the second rate is higher than the first rate.Type: ApplicationFiled: December 21, 2012Publication date: June 26, 2014Applicant: ATI TECHNOLOGIES ULCInventors: Natale Barbiero, Gordon Caruk
-
Publication number: 20140035936Abstract: Methods and apparatus for providing multiple graphics processing capacity, while utilizing unused integrated graphics processing circuitry on a bridge circuit along with an external or discrete graphics processing unit is disclosed. In particular, a bridge circuit includes an integrated graphics processing circuit configured to process graphics jobs. The bridge circuit also includes an interface operable according to interface with a discrete graphics processing circuit. A controller is included with the bridge circuit and responsive whenever the discrete graphics processing circuit is coupled to the interface to cause the integrated graphics processing circuit to process a task of the graphics job in conjunction with operation of the discrete graphics processing circuit that is operable to process another task of the graphics job. Corresponding methods are also disclosed.Type: ApplicationFiled: June 24, 2013Publication date: February 6, 2014Applicant: ATI TECHNOLOGIES, ULCInventors: Grigori Temkine, Gordon Caruk