Patents by Inventor Gordon D. Holt

Gordon D. Holt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9085461
    Abstract: A wafer having a plurality of dies (also called array chips) on the wafer, the die having an electrode to generate a deprotecting reagent, a working electrode to electrochemically synthesize a material, a confinement electrode adjacent to the working electrode to confine reactive reagents, and a die pad, wherein die pads of the plurality of dies are interconnected on the wafer to electrochemically synthesize the material in parallel on a plurality of working electrodes is disclosed. Also, a method for wafer-scale manufacturing of a plurality of dies and a method for electrochemically synthesizing a material in parallel on a plurality of dies on a wafer are disclosed.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: July 21, 2015
    Assignee: INTEL CORPORATION
    Inventors: Valery M. Dubin, Florian Gstrein, Gordon D. Holt, Brandon Barnett
  • Patent number: 8647821
    Abstract: Described are devices and methods for detecting binding on an electrode surface. In addition, devices and methods for electrochemically synthesizing polymers and devices and methods for synthesizing and detecting binding to the polymer on a common integrated device surface are described.
    Type: Grant
    Filed: December 22, 2012
    Date of Patent: February 11, 2014
    Assignee: Intel Corporation
    Inventors: Hernan A. Castro, Gordon D. Holt, Brandon C. Barnett, Handong Li, Narayanan Sundararajan, Wei Wang
  • Patent number: 8278121
    Abstract: A wafer having a plurality of dies (also called array chips) on the wafer, the die having an electrode to generate a deprotecting reagent, a working electrode to electrochemically synthesize a material, a confinement electrode adjacent to the working electrode to confine reactive reagents, and a die pad, wherein die pads of the plurality of dies are interconnected on the wafer to electrochemically synthesize the material in parallel on a plurality of working electrodes is disclosed. Also, a method for wafer-scale manufacturing of a plurality of dies and a method for electrochemically synthesizing a material in parallel on a plurality of dies on a wafer are disclosed.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: October 2, 2012
    Assignee: Intel Corporation
    Inventors: Valery M. Dubin, Florian Gstrein, Gordon D. Holt, Brandon Barnett
  • Publication number: 20120225512
    Abstract: A wafer having a plurality of dies (also called array chips) on the wafer, the die having an electrode to generate a deprotecting reagent, a working electrode to electrochemically synthesize a material, a confinement electrode adjacent to the working electrode to confine reactive reagents, and a die pad, wherein die pads of the plurality of dies are interconnected on the wafer to electrochemically synthesize the material in parallel on a plurality of working electrodes is disclosed. Also, a method for wafer-scale manufacturing of a plurality of dies and a method for electrochemically synthesizing a material in parallel on a plurality of dies on a wafer are disclosed.
    Type: Application
    Filed: May 16, 2012
    Publication date: September 6, 2012
    Inventors: Valery M. Dubin, Florian Gstrein, Gordon D. Holt, Brandon Barnett
  • Publication number: 20120070930
    Abstract: A wafer having a plurality of dies (also called array chips) on the wafer, the die having an electrode to generate a deprotecting reagent, a working electrode to electrochemically synthesize a material, a confinement electrode adjacent to the working electrode to confine reactive reagents, and a die pad, wherein die pads of the plurality of dies are interconnected on the wafer to electrochemically synthesize the material in parallel on a plurality of working electrodes is disclosed. Also, a method for wafer-scale manufacturing of a plurality of dies and a method for electrochemically synthesizing a material in parallel on a plurality of dies on a wafer are disclosed.
    Type: Application
    Filed: September 23, 2011
    Publication date: March 22, 2012
    Inventors: Valery M. DuBin, Florian Gstrein, Gordon D. Holt, Brandon Barnett
  • Patent number: 8053774
    Abstract: A wafer having a plurality of dies (also called array chips) on the wafer, the die having an electrode to generate a deprotecting reagent, a working electrode to electrochemically synthesize a material, a confinement electrode adjacent to the working electrode to confine reactive reagents, and a die pad, wherein die pads of the plurality of dies are interconnected on the wafer to electrochemically synthesize the material in parallel on a plurality of working electrodes is disclosed. Also, a method for wafer-scale manufacturing of a plurality of dies and a method for electrochemically synthesizing a material in parallel on a plurality of dies on a wafer are disclosed.
    Type: Grant
    Filed: June 6, 2005
    Date of Patent: November 8, 2011
    Assignee: Intel Corporation
    Inventors: Valery M. Dubin, Florian Gstrein, Gordon D. Holt, Brandon Barnett
  • Patent number: 7387607
    Abstract: A monitoring device having a signal receiver, a pseudo-ground, a digital processor and a transceiver, the signal receiver having an ability to receive a sensed signal representing a patient vital sign, the pseudo-ground having an ability to generate a baseline signal that is compared with the sensed signal, the transceiver having an ability to wirelessly transmit a processed signal from the digital processor to a base station or a wireless gateway and to receive an incoming signal from the base station or the wireless gateway, and the digital processor having an ability to process the sensed signal and the incoming signal locally within the monitoring device is disclosed.
    Type: Grant
    Filed: June 6, 2005
    Date of Patent: June 17, 2008
    Assignee: Intel Corporation
    Inventors: Gordon D. Holt, Brandon Barnett, Richard Wykoff, Sorin Davidovici, Xiao-Feng Qi
  • Patent number: 6683076
    Abstract: Methods for treatment of disorders associated with glycolipid accumulation, such as Niemann-Pick Type C (NPC) disease, comprising administering a therapeutically effective amount of an inhibitor of glucosylceramide synthesis. Inhibitors of glucosylceramide synthesis include N-butyldeoxynojirimycin, N-butyldeoxygalactonojirimycin, and N-nonyldeoxynojirimycin; 1-phenyl-2-decanoylamino-3-morpholino-1-propanol (PDMP), D-threo-1-phenyl-2-decanoylamino-3-morpholino-1-propanol and structurally related analogues thereof; and agents capable of increasing the rate of neuronal glycolipid degradation.
    Type: Grant
    Filed: October 19, 2001
    Date of Patent: January 27, 2004
    Assignee: Oxford Glyco-Sciences (UK) Ltd
    Inventors: Steven Walkley, Gordon D. Holt
  • Publication number: 20020115667
    Abstract: Methods for treatment of disorders associated with glycolipid accumulation, such as Niemann-Pick Type C (NPC) disease, comprising administering a therapeutically effective amount of an inhibitor of glucosylceramide synthesis. Inhibitors of glucosylceramide synthesis include N-butyldeoxynojirimycin, N-butyldeoxygalactonojirimycin, and N-nonyldeoxynojirimycin; 1-phenyl-2-decanoylamino-3-morpholino-1-propanol (PDMP), D-threo-1-phenyl-2-decanoylamino-3-morpholino-1-propanol and structurally related analogues thereof; and agents capable of increasing the rate of neuronal glycolipid degradation.
    Type: Application
    Filed: October 19, 2001
    Publication date: August 22, 2002
    Inventors: Steven Walkley, Gordon D. Holt