Abstract: A system and method for processing digital images that efficiently buffers pixel data relating to digital images is disclosed. Pixel values are read from an image storage memory and temporarily stored in a buffer memory according to a non-raster pattern. The processing of pixels also occurs according to a more efficient non-raster patter.

Abstract: The present disclosure describes apparatuses and techniques for low-power alternate firmware. In some aspects, data packets are received from a network interface via a reduced-feature-set network stack implemented on a subset of hardware. The reduced-feature-set network stack is used to respond to some of the data packets. When a determination is made that the reduced-feature-set network stack is not capable of responding to others of the data packets, an increased-feature-set network stack is implemented via another subset of the hardware.

Abstract: In one example, a direct memory access controller includes a memory interface, a requestor interface, and an address generator. The memory interface is configured to cause a memory to provide at least a subset of data stored in the memory. The requestor interface is configured to receive a request for a consecutively addressed subset of the data stored in the memory to be provided in a non-consecutive order. The address generator is in communication with the requestor interface and the memory interface. The address generator is configured to, based on the request, sequentially generate non-consecutive addresses of the requested subset of the data to cause the memory to provide the requested subset of data in the requested non-consecutive order.

Abstract: A method for printing on a print medium, where the method comprises receiving, into a printing apparatus, a print medium containing preprinted information located on a first portion of the print medium. The method further comprises the printing apparatus printing information on a second portion of the print medium, wherein the second portion is different from the first portion. The method also comprises the printing apparatus marking an indication on the print medium at or near the first portion of the print medium, wherein the indication identifies the preprinted information located on the first portion of the print medium as being distinct from the information located on the second portion of the print medium.

Abstract: A system and method for processing digital images that efficiently buffers pixel data relating to digital images is disclosed. Pixel values are read from an image storage memory and temporarily stored in a buffer memory according to a non-raster pattern. The processing of pixels also occurs according to a more efficient non-raster pattern.

Abstract: The disclosed embodiments relate to a memory controller for retrieving a plurality of data stored in a memory in communication with the memory controller, the plurality of data being characterized by a first arrangement of first and second non-parallel arrays, such as one-dimensional arrays. The first array comprises at least first and second data of the plurality of data and the second array comprises at least the first data and third data of the plurality of data. The memory is operative to provide the at least first and second data of the first array before providing at least the third data of the second array when the memory is accessed based on an address of the first data in the memory and an amount of the plurality of data to provide starting from the address of the first data.

Abstract: A system is provided for scaling image data comprising a Direct Memory Access (DMA) engine adapted to read the image data from a horizontal pixel strip in a column-by-column format, a scaling block adapted to scale the image data read by the read DMA engine into scaled column output data, and a buffer memory for storing the scaled column output data for the horizontal pixel strip. A method is also provided for scaling an image comprising reading pixel values from a pixel strip in a column-by-column manner across the pixel strip and scaling the pixel values for each column to produce scaled column output data. The scaled column output data for a plurality of columns is then read and the scaled column output data is scaled from the plurality of columns to produce scaled row output data for a row of pixels.

Abstract: A system is provided for scaling image data comprising a Direct Memory Access (DMA) engine adapted to read the image data from a horizontal pixel strip in a column-by-column format, a scaling block adapted to scale the image data read by the read DMA engine into scaled column output data, and a buffer memory for storing the scaled column output data for the horizontal pixel strip. A method is also provided for scaling an image comprising reading pixel values from a pixel strip in a column-by-column manner across the pixel strip and scaling the pixel values for each column to produce scaled column output data. The scaled column output data for a plurality of columns is then read and the scaled column output data is scaled from the plurality of columns to produce scaled row output data for a row of pixels.

Abstract: A bus architecture includes master devices that are each capable of initiating a data transfer procedure by generating a bus request signal. Each of the master devices is arranged to transmit an address signal to an address input of a multiplexer, to transmit a data signal to a data input of the multiplexer, and to transmit a control signal to a control input of the multiplexer. The control signals may include burst type control signals. The multiplexer is capable of selectively coupling a selected master device chosen from the group consisting of the master devices to a bus. The bus architecture further includes an arbiter arranged to receive the bus request signals as first inputs and arranged to receive the burst type control signals as second inputs, where the burst type control signals are received from an ingress side of the multiplexer.

Abstract: A mass storage device motherboard or secondary board includes a bridging circuit. The bridging circuit converts signals from the mass storage device into USB signals. The bridging circuit can be provided by a chip that converts ATA/ATAPI signals into USB signals.

Abstract: A system on a chip (SOC) bus architecture may comprise a plurality of masters operable to request communications over a AMBA-type bus. An arbiter may receive requests and burst control signals directly from the masters. The arbiter may determine a burst length associated with a request and may also grant a master allowance to access the bus. The arbiter may configure a multiplexer to couple the granted master to the bus dependent on the determined burst length.

Abstract: A mass storage device motherboard or secondary board includes a bridging circuit. The bridging circuit converts signals from the mass storage device into USB signals. The bridging circuit can be provided by a chip that converts ATA/ATAPI signals into USB signals.

Abstract: A communication system is presented whereby sequences of video screens sent from a host CPU to a video controller can be stored and subsequently retrieved by a terminal located remote from the host CPU. The host CPU and video controller form part of a server arranged within a distributed computing system. An administrator situated at the remote terminal can retrieve select video screens produced during server operations to determine information regarding the server configuration and possible causes of server failure or future failure. The sequence of video screens thereby represent video screen changes stored upon a server controller adapted for coupling to the server expansion bus. The video screen changes represent a sequence of video screen changes occurring prior to server failure or after server reset. Those changes provide beneficial information to an administrator located remote from the server, and allows the administrator to communicate with the server using several possible communication protocols.

Abstract: A communication system is presented whereby sequences of video screens sent from a host CPU to a video controller can be stored and subsequently retrieved by a terminal located remote from the host CPU. The host CPU and video controller form part of a server arranged within a distributed computing system. An administrator situated at the remote terminal can retrieve select video screens produced during server operations to determine information regarding the server configuration and possible causes of server failure or future failure. The sequence of video screens thereby represent video screen changes stored upon a server controller adapted for coupling to the server expansion bus. The video screen changes represent a sequence of video screen changes occurring prior to server failure or after server reset. Those changes provide beneficial information to an administrator located remote from the server, and allows the administrator to communicate with the server using several possible communication protocols.

Abstract: A printed circuit board includes an edge connector operable to be coupled to an expansion bus. An integrated circuit is mounted on the printed circuit board and is coupled to the edge connector. The integrated circuit is operable to snoop memory operations on the expansion bus and cause selected memory data to be stored in a memory on the printed circuit board. A first power conductor extends across a first portion of the printed circuit board and is coupled to the integrated circuit. A second power conductor extends across a second portion of the printed circuit board and is also coupled to the integrated circuit. The circuit board also includes a decoupling unit connected between the first power conductor and the second power conductor. The decoupling unit causes disconnect of the first power conductor from the second power conductor during times in which voltage within the first power conductor is less than voltage within the second power conductor.

Abstract: A communication system is presented whereby sequences of video screens sent from a host CPU to a video controller can be stored and subsequently retrieved by a terminal located remote from the host CPU. The host CPU and video controller form part of a server arranged within a distributed computing system. An administrator situated at the remote terminal can retrieve select video screens produced during server operations to determine information regarding the server configuration and possible causes of server failure or future failure. The sequence of video screens thereby represent video screen changes stored upon a server controller adapted for coupling to the server expansion bus. The video screen changes represent a sequence of video screen changes occurring prior to server failure or after server reset. Those changes provide beneficial information to an administrator located remote from the server, and allows the administrator to communicate with the server using several possible communication protocols.

Abstract: A communication system is presented whereby sequences of video screens sent from a host CPU to a video controller can be stored and subsequently retrieved by a terminal located remote from the host CPU. Detection logic, controller memory, processor and a communication unit are compiled as a system configured upon a PCB. The PCB is configured to maintain certain vital functions even if power supplied from an expansion bus ceases. The PCB may employ a battery which maintains processor and controller memory activities and communication therebetween for a period of time sufficient to sustain video screen information stored within the controller memory. Thus, decoupling circuitry is present which prevents drain upon the battery if the communication unit is not being used. The decoupling unit separates power and signal conductors between portions of the printed circuit board.