Abstract: A method for performing latency optimization on a system design to be implemented on a target device includes inserting a variable latency indicator in the system design at a place where latency can be varied. The system design includes pipeline registers at the place where the variable latency indicator is inserted. Latency optimization is then automatically performed on the system design, during a computer aided design flow performed by an electronic Design Automation (EDA) tool, by varying the number of the pipeline registers at the variable latency indicator to obtain optimized latency without affecting system performance of the system design.

Abstract: An integrated circuit may include memory interface circuitry for communicating with off-chip memory. The memory interface circuitry may receive data signals and data strobe signals from different memory devices via respective data ports and data strobe ports. The memory interface circuitry may be operable in at least first and second modes. In the first mode, data signals from each memory device may be received at two respective data ports while the data strobe signal from one memory device is used to clock the data signals at two corresponding read capture registers. In the second mode, data signals from first and second memory devices may be received via first and second data ports, respectively. The data strobe signal from the first memory device may be ignored while the data strobe signal from the second memory device is used to clock the data signals at two corresponding read capture registers.

Abstract: A method for designing a system on a target device includes entering the system. The system is synthesized. The system is mapped. The system is placed on the target device. The system is routed. Physical synthesis is performed on the system immediately after more than one of the entering, synthesizing, mapping, placing and routing procedures.

Abstract: A logic design system operable to configure an integrated circuit device using custom logic design data is disclosed. The disclosed logic design system includes a computer-aided design tool that may be used to determine a memory space estimate based on a custom logic design data analysis. A memory size analysis may be performed on the custom logic design data to determine the maximum amount of stack memory that is required to execute procedures in the device. The logic design system may also monitor for changing memory requirements of the custom logic design. The logic design system may configure the device with the custom logic design data based on the memory space estimate.

Abstract: A programmable circuit includes a physical interface at an input output (IO) periphery of the programmable circuit. The programmable circuit also includes a partial reconfigurable (PR) module, at the IO periphery of the programmable circuit, to implement a sequencer unit operable to configure the physical interface during a first instance of the PR module, and a controller unit operable to translate commands to the physical interface during a second instance of the PR module.

Abstract: A method for designing a system on a target device includes entering the system. The system is synthesized. The system is mapped. The system is placed on the target device. The system is routed. Physical synthesis is performed on the system immediately after more than one of the entering, synthesizing, mapping, placing and routing procedures.

Abstract: Mechanisms for measuring, analyzing, and presenting performance data associated with a memory controller system are described. The mechanisms include a performance monitor that detects and analyzes performance including efficiency and latency of a memory controller system. In addition to determining performance, the systems identifies reasons for loss of memory controller system efficiency. Moreover, the reasons, the efficiency, and the latency are analyzed and presented in a manner easily understandable to a user.

Abstract: A method for designing a system on a target device includes synthesizing the system. The system is mapped. The system is placed on the target device. Physical synthesis is performed on the system by identifying a plurality of register retiming solutions for each register in the system, performing combinational resynthesis on each of the register retiming solutions, and selecting a combinational resynthesis solution for the system.

Abstract: Systems and methods for using memory commands are described. The systems include a memory controller. The memory controller receives a plurality of user transactions. The memory controller converts each user transaction into one or more row and column memory commands. The memory controller reorders the memory commands associated with the plurality of user transactions before sending the memory commands to a memory device.

Abstract: A method for optimizing a system on a target device is disclosed. A LUT is unpacked to form a plurality of LUTs of a smaller size upon determining that the unpacking can satisfy one or more predefined objectives. The plurality of LUTs are repacked such that the design for the system is improved. Other embodiments are disclosed.

Abstract: A method for designing a system on a target device includes entering the system. The system is synthesized. The system is mapped. The system is placed on the target device. The system is routed. Physical synthesis is performed on the system immediately after more than one of the entering, synthesizing, mapping, placing and routing procedures.

Abstract: A method for improving a maximum operating frequency of an integrated circuit including a first shift register within a first random access memory (RAM) block is described. The method includes improving the maximum operating frequency by finding the first shift register implemented within the first RAM block.

Abstract: A method for designing a system on a target device includes synthesizing the system. The system is placed on the target device. Optimizing placement of the system for routing is performed after placing the system. The system is routed after optimizing placement.

Abstract: A method for designing a system on a target device includes synthesizing the system. The system is mapped. The system is placed on the target device. The system is routed. Physical synthesis is performed on the system where a first descendant thread is spawned to run in parallel with an existing thread where the first descendant thread is executing a different optimization strategy than the existing thread but on a same netlist as the existing thread.