Abstract: A method for operating plurality of DSL modem transmitters integrated within a circuit card. The method includes each DSL modem transmitter: generating a full power physical frame when the DSL modem transmitter is provided with data to transmit; generating a low power physical frame having a control channel signal component and no data; and selecting between the full power physical frame and the low power physical frame for transmission from the DSL modem transmitter, wherein selection of the low power physical frame for transmission from the DSL modem transmitter is based only on the DSL modem transmitter having no data to transmit. The method further includes limiting aggregate flow of data to the plurality of DSL modem transmitters such that a total power required by the plurality of DSL modem transmitters is held below a predefined target power level.

Abstract: A method and system for encoding a set of range labels for each parameter field in a packet classification key in such a way as to require preferably only a single entry per rule in a final processing stage of a packet classifier. Multiple rules are sorted accorded to their respective significance. A range, based on a parameter in the packet header, is previously determined. Multiple rules are evaluated according to an overlapping of rules according to different ranges. Upon a determination that two or more rules overlap, each overlapping rule is expanded into multiple unique segments that identify unique range intersections. Each cluster of overlapping ranges is then offset so that at least one bit in a range for the rule remains unchanged. The range segments are then converted from binary to Gray code, which results in the ability to determine a CAM entry to use for each range.

Abstract: A generic method and apparatus for managing semaphores in a multi-threaded processing system has a storage area for each of the threads in the processing system. Each storage area includes a first part for storing at least one indicia for identifying at least one unique semaphore from a plurality of semaphores utilized by the multi-threaded processing system and a second part for storing an indicia for indicating a locked status for the stored semaphore. A thread requiring a semaphore sends a semaphore lock request to the semaphore manager which examines the contents of all of the storage areas to determine the status of the requested semaphore. If the requested semaphore is not locked, it is locked for the requesting thread by inserting the requested semaphore and locked status in the memory location assigned to the requesting thread.

Abstract: The decision within a packet processing device to transmit a newly arriving packet into a queue to await further processing or to discard the same packet is made by a flow control method and system. The flow control is updated with a constant period determined by storage and flow rate limits. The update includes comparing current queue occupancy to a threshold. The outcome of the update is adjustment up or down of the transmit probability value. The value is stored for the subsequent period of flow control and packets arriving during that period are subject to a transmit or discard decision that uses that value.

Abstract: A system and method of protocol and frame classification in a system for data processing is disclosed, including, analyzing a portion of the, packet or frame according to predetermined tests, and storing characteristics of the packet for use in subsequent processing of the frame. The characteristics are preferably obtained with hardware, which does so quickly and in a uniform time period. The stored characteristics of the packet are then used by the network processing complexes in further processing of the frame. The processor is preconditioned with a starting instruction address or cede entry point and the location of the beginning of the layer 3 header as well as flags for the type of frame.

Abstract: A method and structure is disclosed for dispatching appropriate data to a network processing system comprising an improved technique for extracting protocol header fields for use by the network processor. This technique includes basic classification of a packet according to the types of protocol headers present in the packet. Based on the results of the classification, specific parameter fields are extracted from corresponding headers. All such parameter fields from one or more protocol headers in the packet are concatenated into a compressed dispatch message. Multiple of such dispatch messages are bundled into a single composite dispatch message. Thus selected header fields from N packets are passed to the network processor in a single composite dispatch message, increasing the network processor's packet forwarding capacity by a factor of N. Likewise, multiple enqueue messages are bundled into a single composite enqueue message to direct enqueue and frame alterations to be taken on the bundle of N packets.

Abstract: The decision within a packet processing device to transmit a newly arriving packet into a queue to await further processing or to discard the same packet is made by a flow control method and system. The flow control is updated with a constant period determined by storage and flow rate limits. The update includes comparing current queue occupancy to a threshold. The outcome of the update is adjustment up or down of the transmit probability value. The value is stored for the subsequent period of flow control and packets arriving during that period are subject to a transmit or discard decision that uses that value.

Abstract: Systems and methods for distributing thread instructions in the pipeline of a multi-threading digital processor are disclosed. More particularly, hardware and software are disclosed for successively selecting threads in an ordered sequence for execution in the processor pipeline. If a thread to be selected cannot execute, then a complementary thread is selected for execution.

Abstract: A method and structure is disclosed for dispatching appropriate data to a network processing system comprising an improved technique for extracting protocol header fields for use by the network processor. This technique includes basic classification of a packet according to the types of protocol headers present in the packet. Based on the results of the classification, specific parameter fields are extracted from corresponding headers. All such parameter fields from one or more protocol headers in the packet are concatenated into a compressed dispatch message. Multiple of such dispatch messages are bundled into a single composite dispatch message. Thus selected header fields from N packets are passed to the network processor in a single composite dispatch message, increasing the network processor's packet forwarding capacity by a factor of N. Likewise, multiple enqueue messages are bundled into a single composite enqueue message to direct enqueue and frame alterations to be taken on the bundle of N packets.

Abstract: A structure and technique for preventing collisions using a hash table in conjunction with a CAM to identify and prevent collision of binary keys. A portion of the hash value of a binary key, which does not collide with a portion of the hash value of any other reference binary key, is used as an entry in the hash table. If two or more binary keys have identical values of the portions of the hash values, each of these binary keys are stored in their entirety, in the CAM. The key in the CAM provides a pointer to a data structure where the action associated with that binary key is stored. If the binary key is not found in the CAM, the binary key is hashed, and a specific entry in the hash table is selected using a portion of this hash value.

Abstract: A prefetch mechanism using prefetch attributes is disclosed. In one aspect, an explicit request for data stored in a memory is provided, and a prefetch attribute in a page table entry associated with the explicit request is examined to determine whether to provide one or more prefetch requests based on the prefetch attribute. Another aspect includes determining dynamic prefetch attributes for use in prefetching data, in which prefetch attributes are adjusted based on memory access requests that target next sequential blocks of memory relative to the most recent previous access in a page of memory.

Abstract: A prefetch mechanism using prefetch attributes is disclosed. In one aspect, an explicit request for data stored in a memory is provided, and a prefetch attribute in a page table entry associated with the explicit request is examined to determine whether to provide one or more prefetch requests based on the prefetch attribute. Another aspect includes determining dynamic prefetch attributes for use in prefetching data, in which prefetch attributes are adjusted based on memory access requests that target next sequential blocks of memory relative to the most recent previous access in a page of memory.

Abstract: A low power DSL modem transmitter, suitable for incorporation in integrated DSLAM server line cards, transmits full power physical frames which include a control channel and a data field when data is available for transmission and physical frames having only a control channel or a control channel and a low power synchronization field when data is not available for transmission. And a method for controlling the total power dissipated in the integrated DSLAM by selectively restricting the flaw of data packets to the DSLs.

Abstract: A structure and technique for preventing collisions using a hash table in conjunction with a CAM to identify and prevent collisions of binary keys. A portion of the hash value of a binary key, which does not collide with a portion of the hash value of any other reference binary key, is used as an entry in the hash table. If two or more binary keys have identical values of the portions of the hash values, each of these binary keys are stored in their entirety, in the CAM. The key in the CAM provides a pointer to a data structure where the action associated with that binary key is stored. If the binary key is not found in the CAM, the binary key is hashed, and a specific entry in the hash table is selected using a portion of this hash value.

Abstract: A page table mechanism translates virtual addresses to real addresses. In a first aspect, page table entries are contained in equal-sized blocks, the entries within each block corresponding to contiguous pages of virtual address space. Preferably, the common high-order portion of the virtual address is contained in segments distributed among multiple page table entries of the block. In a second aspect, the virtual address indexes a binary tree definitional structure. Decode logic traverses a binary tree defined by the definitional structure by testing selective bits of the virtual address to reach a leaf of the binary tree, which defines the location of data defining the real address.

Abstract: A method, computer program product and system for facilitating inter-digital signal processing (DSP) data communications. A direct memory access (DMA) controller may be configured to facilitate transfers of data between a first and a second DSP processor core coupled to the DMA controller. The DMA controller may read a data structure, referred to as a “buffer descriptor block,” to perform the data transfer. The buffer descriptor block may store both a source address and a destination address indicating where the data is to be retrieved and stored. The buffer descriptor block may further store a value, e.g., number of bytes, indicating a size of the data to be transferred. The DMA controller may then transfer the data located at the source address in the first DSP processor core, with a size, e.g., number of bytes, indicated from the buffer descriptor block, to the destination address in the second DSP processor core.

Abstract: A method and system for identifying sessions in a computer network is disclosed. The session is between a first computer system and a second computer system. The session consists of an exchange of a plurality of packets between the computer systems. Each of the packets includes source information and destination information relating to the first computer system and the second computer system. The method and system include providing a symmetric key and identifying the session using the symmetric key. The symmetric key is provided utilizing a manipulation of the source information and the destination information. The symmetric key is associated with the plurality of packets traveling between the first computer system and the second computer system.

Abstract: A method and system for messaging between processors and co-processors connected through a bus. The method permits a multi-thread system processor to request the services of a processor or co-processor located on the bus. Message control blocks are stored in a memory which identify the physical address of the target processor, as well as a memory location in the memory dedicated to the thread requesting the service. When the system processor requests service of a processor or co-processor, a DCR command is created pointing to the message control block. A message is built from information contained in the message control block or transferred to the processor or co-processor. The return address for the processor or co-processor message is concatenated with the thread number, so that the processor or co-processor can create a return message specifically identifying memory space dedicated to the requesting thread for storage of the response message.

Abstract: A method and system for compressing and transmitting data using asynchronous transfer mode (ATM) is disclosed. The data include a plurality of segments. Each of the plurality of segments has a first end and a second end. In one aspect, the method and system include representing the first end of a segment with a partition compression code word and compressing a remaining portion of the segment. The method and system could also combine the marking of the boundary and subsequent data into a compound compression code word. In another aspect, the method and system include representing the first end of a segment with a transparent mode command, transmitting the transparent mode command, and transmitting a remaining portion of the segment.

Abstract: A method and system for identifying a data structure associated with a packet of data. A processor internal to a packet processor may extract one or more fields in a packet header field of a received packet of data to generate a search key. The internal processor may then be configured to select which table, e.g., routing table, quality of service table, filter table, needs to be accessed using the search key in order to process the received packet of data. A determination may then be made by the internal processor as to whether a CAM or a hash table and a Patricia Tree are used to identify the data structure associated with the received packet of data. Based on table definitions in a register, the internal processor may make such a determination.