Abstract: A low dropout (LDO) voltage regulator includes a first LDO stage that receives a first supply voltage and is active during a first time interval and a second LDO stage that receives a second supply voltage and is active during a second time interval. An operational amplifier receives a feedback voltage based on the LDO output voltage and provides an amplified feedback signal to the first and second LDO stages. A compensation capacitor is selectively coupled between the operational amplifier and either the first or the second LDO stage. A current limit circuit includes a sense FET coupled to the LDO pass FET, a drain voltage replication circuit coupled between the pass FET and sense FET to provide a sense current is indicative of load current when the pass FET is in a linear region, and a current comparator to compare the sense current to a predetermined current level.

Abstract: A low dropout (LDO) voltage regulator includes a first LDO stage that receives a first supply voltage and is active during a first time interval and a second LDO stage that receives a second supply voltage and is active during a second time interval. An operational amplifier receives a feedback voltage based on the LDO output voltage and has an output at which an amplified feedback signal is provided to both the first and second LDO stages. A compensation capacitor is selectively coupled between the operational amplifier and either the first LDO stage or the second LDO stage. A current limit circuit includes a sense FET having a gate coupled to the gate of the LDO pass FET, a drain voltage replication circuit coupled between the drains of the pass FET and sense FET to replicate the pass FET drain voltage so that the sense current is indicative of load current when the pass FET is in a linear region, and a current comparator to compare the sense current to a predetermined current level.