Abstract: In a receiver for signals in a multilevel partial response class-IV communication system, the coefficients of a digital adaptive equalizer need to be updated to minimize the error due to noise and signal distortion. After initial convergence of the equalizer coefficients to near-optimum settings, an estimate of the mean-square error gradient for coefficient updating can be obtained in decision-directed mode from an estimate of the error signal. In the absence of a reference signal, initial convergence must be achieved in self-training mode. The decision-directed error signal is then replaced by a pseudo-error signal for the computation of an approximation of the mean-square error gradient. The invention provides a particular self-training procedure which outperforms known methods in terms of speed of convergence and achieved mean-square error values, and does not require timing recovery prior to equalizer convergence.

Abstract: The start-up time for typical current generation modems for full-duplex data transmission over the Public Switched Telephone Network (PSTN) as specified in CCITT Recommendations V.32 and V.32bis is about 4 to 8 seconds. This invention reduces that start-up time to about 0.5 to 1 second by applying interleaved and overlapping sending and receiving operations of two connected modems, the calling modem and the answering modem. Both modems send and receive simultaneously in a predetermined sequence at different frequency ranges, channel probing tones (e.g. for evaluating the channel bandwidth), repetitive identification messages (e.g. for determining reference times, identifying modulation rates and center frequencies), repetitive response messages (e.g. for transmitting the determined bandwidths and reference times to the other modem and determining round-trip delays), and training sequences (e.g. for determining echoes, frequency shifts, and receiver settings).

Abstract: In a signal processor computing arrangement comprising an ALU (11) and a multiplier (21), two selectively usable accumulators (37, 41) and gating circuitry (61, 63) are provided to allow alternating computation and accumulation of product terms for two output values with sets of input values that overlap. This saves memory accesses by using the same operand twice for different output values, and requires only one processor cycle per partial term and output value. A specific pipeline multiplier (21) is provided consisting of two partial sections (29, 31) with an intermediate pipeline register (33) to allow applying a second set of input operands while computation of the product of a first set of operands is still in progress.

Abstract: In a receiver for PSK modulated signals, carrier phase tracking is achieved by a feedback loop comprising a phase error predictor. Means are provided for adaptively setting the gain factor in the phase error predictor to an optimum value, in response to successive residual phase errors.