Patents by Inventor Goutam Chattopadhyay

Goutam Chattopadhyay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240014568
    Abstract: A metal-only flat metasurface antenna is described. The antenna includes a pillbox beamformer combined with a metasurface structure provided by an array of non-resonant subwavelength unit elements having opening sizes that are strictly smaller than half of the guided-mode wavelength. The pillbox beamformer includes bottom and top parallel plate waveguides (PWPs) forming respective bottom and top cavities for propagation of the guided-mode. Bottom, middle and top metal plates form the two PWPs. Arranged at one end of the bottom and top PWPs is a respective parabolic structure. An all-metal horn structure is centrally arranged at a second end of the bottom PWP opposite the parabolic structure. According to one aspect, the horn structure includes a single feed port arranged at a focal point of the parabolic structure. According to another aspect, the horn structure includes two feed ports arranged at an offset of the focal point.
    Type: Application
    Filed: July 6, 2023
    Publication date: January 11, 2024
    Inventors: Nacer E. CHAHAT, Gaurangi GUPTA, John L. WOLFF, Adrian J. TANG, Goutam CHATTOPADHYAY
  • Patent number: 11824247
    Abstract: A set of antenna geometries for use in integrated arrays at terahertz frequencies are described. Two fabrication techniques to construct such antennas are presented. The first technique uses an advanced laser micro-fabrication, allowing fabricating advanced 3D geometries. The second technique uses photolithographic processes, allowing the fabrication of arrays on a single wafer in parallel.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: November 21, 2023
    Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Goutam Chattopadhyay, Imran Mehdi, Choonsup Lee, John J. Gill, Cecile D. Jung-Kubiak, Nuria Llombart
  • Patent number: 11764450
    Abstract: A phase shifter comprising an actuator coupled to a dielectric. When the dielectric is inserted into the waveguide in response to actuation by the actuator, the phase velocity of the incoming electromagnetic wave is decreased, resulting in a phase shift of the electromagnetic wave. A desired phase shift and a low insertion loss can be controlled by positioning of the dielectric and engineering the permittivity of the dielectric.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: September 19, 2023
    Assignee: California Institute of Technology
    Inventors: Sofia Rahiminejad, Maria A. Del Pino, Cecile D. Jung-Kubiak, Theodore J. Reck, Goutam Chattopadhyay
  • Publication number: 20230027356
    Abstract: Low-loss terahertz switches with nanometer resolution positioning and feedback are disclosed. In one embodiment, the switch uses a U-bend waveguide surrounded by an electromagnetic band gap and is implemented in a fully metal-machined fashion in combination with a piezo-electric motor and an optical linear encoder. In another embodiment, the switch comprises a MEMS device.
    Type: Application
    Filed: June 21, 2022
    Publication date: January 26, 2023
    Applicant: California Institute of Technology
    Inventors: Goutam Chattopadhyay, Robert H. Lin, Sven L. Van Berkel, Sofia Rahiminejad
  • Publication number: 20220407200
    Abstract: A waveguide based variable attenuator device including one or more attenuators each including a porous dielectric material; and a metal coating on the top of the dielectric material; and an actuator coupled to the attenuator. The actuator is configured to position, with nanometer resolution, the one or more attenuators in a waveguide configured and dimensioned to guide an electromagnetic wave having a frequency in a range of 100 gigahertz (GHz) to 1 terahertz (THz). The actuator controls at least one of a position or a volume of the one attenuator inserted in the waveguide to achieve a variable or pre-determined attenuation of the electromagnetic wave transmitted through waveguide.
    Type: Application
    Filed: June 22, 2022
    Publication date: December 22, 2022
    Applicant: California Institute of Technology
    Inventors: Goutam Chattopadhyay, Jacob W. Kooi, Choonsup Lee, Sofia Rahiminejad, Subash Khanal
  • Publication number: 20220267140
    Abstract: A phased array system comprising an array of antennas outputting or receiving electromagnetic radiation to or from a steerable direction, wherein the electromagnetic radiation is at submillimeter wavelengths. The system further comprises a plurality of waveguides outputting or receiving the signals to or from the antennas, each of the waveguides with individual phase tuning. The waveguides are configured and dimensioned to guide an electromagnetic wave comprising the signals having a frequency in a range of 100 gigahertz (GHz) to 1000 terahertz (THz). The system further comprises means for phase shifting the signal by means of shifting or varying one or more phases of the signals relative to one another so as to vary, steer, or scan a direction of the electromagnetic radiation.
    Type: Application
    Filed: February 18, 2022
    Publication date: August 25, 2022
    Applicant: California Institute of Technology
    Inventors: Goutam Chattopadhyay, Cecile D. Jung-Kubiak, Sofia Rahiminejad, Subash Khanal, Sven L. Van Berkel
  • Publication number: 20210013569
    Abstract: A phase shifter comprising an actuator coupled to a dielectric. When the dielectric is inserted into the waveguide in response to actuation by the actuator, the phase velocity of the incoming electromagnetic wave is decreased, resulting in a phase shift of the electromagnetic wave. A desired phase shift and a low insertion loss can be controlled by positioning of the dielectric and engineering the permittivity of the dielectric.
    Type: Application
    Filed: July 7, 2020
    Publication date: January 14, 2021
    Applicant: California Institute of Technology
    Inventors: Sofia Rahiminejad, Maria A. Del Pino, Cecile D. Jung-Kubiak, Theodore J. Reck, Goutam Chattopadhyay
  • Publication number: 20200313271
    Abstract: A set of antenna geometries for use in integrated arrays at terahertz frequencies are described. Two fabrication techniques to construct such antennas are presented. The first technique uses an advanced laser micro-fabrication, allowing fabricating advanced 3D geometries. The second technique uses photolithographic processes, allowing the fabrication of arrays on a single wafer in parallel.
    Type: Application
    Filed: May 19, 2020
    Publication date: October 1, 2020
    Applicant: California Institute of Technology
    Inventors: Goutam Chattopadhyay, Imran Mehdi, Choonsup Lee, John J. Gill, Cecile D. Jung-Kubiak, Nuria Llombart
  • Patent number: 10693210
    Abstract: A set of antenna geometries for use in integrated arrays at terahertz frequencies are described. Two fabrication techniques to construct such antennas are presented. The first technique uses an advanced laser micro-fabrication, allowing fabricating advanced 3D geometries. The second technique uses photolithographic processes, allowing the fabrication of arrays on a single wafer in parallel.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: June 23, 2020
    Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Goutam Chattopadhyay, Imran Mehdi, Choonsup Lee, John J. Gill, Cecile D. Jung-Kubiak, Nuria Llombart
  • Patent number: 10418721
    Abstract: A modulated MTS antenna including a metasurface fabricated from metallized cylinders on a ground plane. The antenna structure can be designed to operate in the Gigahertz or Terahertz frequency band and to have a well defined directivity. The MTS antenna may be micromachined out of a silicon wafer using deep reactive ion etching (DRIE).
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: September 17, 2019
    Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Goutam Chattopadhyay, Cecile D. Jung-Kubiak, Theodore J. Reck, David Gonzalez-Ovejero, Maria Alonso delPino
  • Patent number: 10100858
    Abstract: A silicon alignment pin is used to align successive layer of component made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: October 16, 2018
    Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Cecile Jung-Kubiak, Theodore Reck, Bertrand Thomas, Robert H. Lin, Alejandro Peralta, John J. Gill, Choonsup Lee, Jose V. Siles, Risaku Toda, Goutam Chattopadhyay, Ken B. Cooper, Imran Mehdi
  • Patent number: 10075151
    Abstract: A solid state device chip including diodes (generating a higher frequency output through frequency multiplication of the input frequency) and a novel on-chip power combining design. Together with the on-chip power combining, the chip has increased efficiency because the diodes' anodes, being micro-fabricated simultaneously on the same patch of a GaAs wafer under identical conditions, are very well balanced. The diodes' GaAs heterostructure and the overall chip geometry are designed to be optimized for high power operation. As a result of all these features, the device can generate record-setting power having a signal frequency in the F-band and W-band (30% conversion efficiency).
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: September 11, 2018
    Assignee: California Institute of Technology
    Inventors: Jose Vicente Siles Perez, Choonsup Lee, Goutam Chattopadhyay, Ken B. Cooper, Imran Mehdi, Robert H. Lin, Alejandro Peralta
  • Patent number: 9791321
    Abstract: A multi-pixel terahertz transceiver is constructed using a stack of semiconductor layers that communicate using vias defined within the semiconductor layers. By using a stack of semiconductor layers, the various electrical functions of each layer can be tested easily without having to assemble the entire transceiver. In addition, the design allows the production of a transceiver having pixels set 10 mm apart.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: October 17, 2017
    Assignee: California Institute of Technology
    Inventors: Goutam Chattopadhyay, Ken B. Cooper, Emmanuel Decrossas, John J. Gill, Cecile Jung-Kubiak, Choonsup Lee, Robert Lin, Imran Mehdi, Alejandro Peralta, Theodore Reck, Jose Siles
  • Publication number: 20170288316
    Abstract: A modulated MTS antenna including a metasurface fabricated from metallized cylinders on a ground plane. The antenna structure can be designed to operate in the Gigahertz or Terahertz frequency band and to have a well defined directivity. The MTS antenna may be micromachined out of a silicon wafer using deep reactive ion etching (DRIE).
    Type: Application
    Filed: March 29, 2017
    Publication date: October 5, 2017
    Applicant: California Institute of Technology
    Inventors: Goutam Chattopadhyay, Cecile D. Jung-Kubiak, Theodore J. Reck, David Gonzalez-Ovejero, Maria Alonso delPino
  • Publication number: 20170045065
    Abstract: A silicon alignment pin is used to align successive layer of component made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.
    Type: Application
    Filed: October 28, 2016
    Publication date: February 16, 2017
    Inventors: Cecile JUNG-KUBIAK, Theodore RECK, Bertrand THOMAS, Robert H. LIN, Alejandro PERALTA, John J. GILL, Choonsup LEE, Jose V. SILES, Risaku TODA, Goutam CHATTOPADHYAY, Ken B. COOPER, Imran MEHDI
  • Patent number: 9512863
    Abstract: A silicon alignment pin is used to align successive layers of components made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: December 6, 2016
    Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Cecile Jung-Kubiak, Theodore Reck, Bertrand Thomas, Robert H. Lin, Alejandro Peralta, John J. Gill, Choonsup Lee, Jose V. Siles, Risaku Toda, Goutam Chattopadhyay, Ken B. Cooper, Imran Mehdi
  • Patent number: 9478842
    Abstract: A lens for interconnecting a metallic waveguide with a dielectric waveguide is provided. The lens may be coupled a metallic waveguide and a dielectric waveguide, and minimize a signal loss between the metallic waveguide and the dielectric waveguide.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: October 25, 2016
    Assignee: The United States of America as Represented by the Administrator of the National Aeronautics and Space Administration
    Inventors: Emmanuel Decrossas, Goutam Chattopadhyay, Nacer Chahat, Adrian J. Tang
  • Patent number: 9478843
    Abstract: A system, method, device, and apparatus provide a dielectric waveguide splitter/bi-directional link. A dielectric substrate fabricated into a first Y-junction waveguide with a first port splitting into a first branch leading to a second port and a second branch leading to a third port. An angle between the first branch and the second branch is below ninety degrees (90°). The dielectric waveguide splitter enables millimeter-wave (mmWave) transmission between the first port and the second port while reducing feedback of the mmWave between the second and third port. Two Y-junction waveguides may be fabricated back-to-back to provide simultaneous bidirectional mmWave transmission at a single frequency.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: October 25, 2016
    Assignee: California Institute of Technology
    Inventors: Adrian Joseph Tang, Goutam Chattopadhyay, Nacer E. Chahat, Emmanuel Decrossas
  • Patent number: 9461352
    Abstract: A multi-step silicon etching process has been developed to fabricate silicon-based terahertz (THz) waveguide components. This technique provides precise dimensional control across multiple etch depths with batch processing capabilities. Nonlinear and passive components such as mixers and multipliers waveguides, hybrids, OMTs and twists have been fabricated and integrated into a small silicon package. This fabrication technique enables a wafer-stacking architecture to provide ultra-compact multi-pixel receiver front-ends in the THz range.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: October 4, 2016
    Assignee: California Institute of Technology
    Inventors: Cecile Jung-Kubiak, Theodore Reck, Goutam Chattopadhyay, Jose Vicente Siles Perez, Robert H. Lin, Imran Mehdi, Choonsup Lee, Ken B. Cooper, Alejandro Peralta
  • Publication number: 20160149562
    Abstract: A solid state device chip including diodes (generating a higher frequency output through frequency multiplication of the input frequency) and a novel on-chip power combining design. Together with the on-chip power combining, the chip has increased efficiency because the diodes' anodes, being micro-fabricated simultaneously on the same patch of a GaAs wafer under identical conditions, are very well balanced. The diodes' GaAs heterostructure and the overall chip geometry are designed to be optimized for high power operation. As a result of all these features, the device can generate record-setting power having a signal frequency in the F-band and W-band (30% conversion efficiency).
    Type: Application
    Filed: November 25, 2015
    Publication date: May 26, 2016
    Inventors: Jose Vicente Siles Perez, Choonsup Lee, Goutam Chattopadhyay, Ken B. Cooper, Imran Mehdi, Robert H. Lin, Alejandro Peralta