Abstract: A data processing system architecture is based upon a hardware engine that includes a plurality of functional units and data routing units that interconnect the functional units. The hardware engine performs operations and computations on data as the data traverses paths through the functional units under control of software. The functional units include logic resources, examples of which are flip-flops, latches, arithmetic logic units, random access memory, and the like. The routing units are responsive to the software control signals that are turned on or off to steer the data through these resources. Operations and computations are accomplished according to the steering of the data through the functional units, rather than according to decoding of operation commands that control the functions performed, as typical in the prior art.

Abstract: An integrated multimedia encoding system is disclosed. Multimedia encoders which are capable of adjusting bit rates receive multimedia data to compress the data. After compressing the data, the multimedia encoders adjust the bit rates of the elementary streams responsive to a control input. Bit rates are increased or decreased using delays or, for video data, by allocating more or less bits to each macroblock, frame or group of frames. A unified memory module is coupled to the multimedia encoders to store the multimedia elementary stream data, the Program or Transport stream data, and data from other sources as needed. The unified memory is capable of adjusting storage allocations responsive to the realtime requirements of the incoming multimedia streams and the outgoing Program or Transport stream data.

Abstract: A PCI interface is provided to support a 16- or 32-bit PCI host employing little-endian or big-endian byte ordering. The PCI interface may be arranged on a multiport switch to enable a PCI host to access internal registers and an external memory via a PCI bus. When a 16-bit PCI host is provided with access to a 32-bit internal register, two consecutive 16-bit data transfers are performed. The first 16 bits of data are temporarily stored in a holding register until the following 16 bits are transferred. The PCI host accesses the external memory via posting write buffers and prefetch read buffers arranged between an external memory interface and the PCI interface. When the multiport switch is configured to support a big-endian PCI host, bytes of a word transferred between the external memory and a write or read buffer are swapped to rearrange byte ordering of the word.

Abstract: An apparatus and method of efficiently and dynamically generating the addresses associated with a set of instructions in a microprocessor pipeline is disclosed. Program counter age bits associated with the offsets of an address of a predetermined instruction within a set of instructions are used to indicate the chronological age of each instruction within the set of instructions. The age bits are generated by a logic circuit which also dispatches instructions to various execution units. The age bits are used to maintain and track the addresses of an instruction stream within a processing system so that there is no need to store the addresses of each and every instruction.