Patents by Inventor Graham Allan

Graham Allan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7007706
    Abstract: A shelter structure having a pair of end frames and a canopy frame interconnecting the end frames. There are also provided a plurality of adjustable bracing members interconnecting frame members of the canopy frame. The adjustable bracing members may be tensioned during installation of the shelter structure to stabilize the canopy frame against lateral or transverse forces.
    Type: Grant
    Filed: June 26, 2001
    Date of Patent: March 7, 2006
    Assignee: Weatherstopper Pty Ltd.
    Inventors: Graham Allan Pinnell, Daniel Robert Flynn, Alan Ned Netherway
  • Patent number: 6992950
    Abstract: A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.
    Type: Grant
    Filed: August 21, 2003
    Date of Patent: January 31, 2006
    Assignee: MOSAID Technologies Incorporated
    Inventors: Richard C. Foss, Peter B. Gillingham, Graham Allan
  • Publication number: 20050265506
    Abstract: A clock applying circuit for a synchronous memory is comprised or a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period or the clock input signal.
    Type: Application
    Filed: August 1, 2005
    Publication date: December 1, 2005
    Applicant: Mosaid Technologies, Inc.
    Inventors: Richard Foss, Peter Gillingham, Graham Allan
  • Publication number: 20040130962
    Abstract: A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.
    Type: Application
    Filed: August 21, 2003
    Publication date: July 8, 2004
    Applicant: MOSAID Technologies Incorporated
    Inventors: Richard C. Foss, Peter B. Gillingham, Graham Allan
  • Publication number: 20040112120
    Abstract: A composition capable of supplying ethylene gas to botanical systems is disclosed and includes a microporous solid having a plurality of cells and a quantity of ethylene gas contained within one or more of the plurality of cells. The cells can be either open or closed, and can be either permeable, degradable or both so as to release the ethylene over a period of time. The ethylene gas is released from the cells over a period of time. The release rate of the ethylene gas may be altered by changing the density of the microporous solid. The release rate may also be altered by manipulating the size or shape of the microporous solid.
    Type: Application
    Filed: August 20, 2003
    Publication date: June 17, 2004
    Inventors: Fritz Kramer, G. Graham Allan
  • Publication number: 20040091075
    Abstract: A delay compensation circuit for a delay locked loop which includes a main delay line having a fine delay line comprising fine delay elements and a coarse delay line comprising coarse delay elements, the main delay line being controlled by a controller, the delay compensation circuit comprising: an adjustable fine delay for modeling a coarse delay element, a counter for controlling the adjustable fine delay to a value which is substantially the same as that of a coarse delay element, a circuit for applying a representation of the system clock to the delay compensation circuit, and a circuit for applying the fine delay count from the counter to the controller for adjusting the fine delay line of the main delay line to a value which is substantially the same as that of a coarse delay element of the main delay line.
    Type: Application
    Filed: November 7, 2003
    Publication date: May 13, 2004
    Inventors: Gurpreet Bhullar, Graham Allan
  • Publication number: 20040035455
    Abstract: A shelter structure (10) having a pair of end frames (11) and a canopy frame (12) interconnecting the end frames (11). There are also provided a plurality of adjustable bracing members (19) interconnecting frame members (13, 16, 18) of the canopy frame (12). The adjustable bracing members (19) may be tensioned during installation of the shelter structure (10) to stabilise the canopy frame (12) against lateral or transverse forces.
    Type: Application
    Filed: June 26, 2003
    Publication date: February 26, 2004
    Inventors: Graham Allan Pinnell, Daniel Robert Flynn, Alan Ned Netherway
  • Patent number: 6683928
    Abstract: A delay compensation circuit for a delay locked loop which includes a main delay line having a fine delay line comprising fine delay elements and a coarse delay line comprising coarse delay elements, the main delay line being controlled by a controller, the delay compensation circuit comprising: an adjustable fine delay for modeling a coarse delay element, a counter for controlling the adjustable fine delay to a value which is substantially the same as that of a coarse delay element, a circuit for applying a representation of the system clock to the delay compensation circuit, and a circuit for applying the fine delay count from the counter to the controller for adjusting the fine delay line of the main delay line to a value which is substantially the same as that of a coarse delay element of the main delay line.
    Type: Grant
    Filed: October 3, 2001
    Date of Patent: January 27, 2004
    Assignee: Mosaid Technologies Incorporated
    Inventors: Gurpreet Bhullar, Graham Allan
  • Patent number: 6657919
    Abstract: A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: December 2, 2003
    Assignee: MOSAID Technologies Incorporated
    Inventors: Richard C. Foss, Peter B. Gillingham, Graham Allan
  • Patent number: 6657918
    Abstract: A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.
    Type: Grant
    Filed: October 23, 2002
    Date of Patent: December 2, 2003
    Assignee: Mosaid Technologies Incorporated
    Inventors: Richard C. Foss, Peter B. Gillingham, Graham Allan
  • Publication number: 20030107944
    Abstract: A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.
    Type: Application
    Filed: January 17, 2003
    Publication date: June 12, 2003
    Applicant: Mosaid Technologies Incorporated
    Inventors: Richard C. Foss, Peter B. Gillingham, Graham Allan
  • Publication number: 20030090952
    Abstract: A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.
    Type: Application
    Filed: October 23, 2002
    Publication date: May 15, 2003
    Inventors: Richard C. Foss, Peter B. Gillingham, Graham Allan
  • Patent number: 6538911
    Abstract: An invention is disclosed for a content addressable memory (CAM) with a block select for power management. The CAM includes a plurality of memory blocks for storing data addressable within the CAM, and a search port in communication with the plurality of memory blocks. The search port is capable of facilitating search operations using the memory blocks. Also included in the CAM is a block select bus capable of selecting at least one specific memory block from the plurality of memory blocks. By using the block select bus, the search operations are performed using only the selected memory blocks. Similar to search operations, the block select signal or a similar signal can also be used to select specific memory blocks, wherein maintenance operations are performed using only the selected memory blocks.
    Type: Grant
    Filed: August 24, 2001
    Date of Patent: March 25, 2003
    Assignee: SiberCore Technologies, Inc.
    Inventors: Graham A. Allan, G. F. Randall Gibson, Jason Edward Podaima
  • Publication number: 20020075747
    Abstract: A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.
    Type: Application
    Filed: October 12, 2001
    Publication date: June 20, 2002
    Applicant: MOSAID Technologies Incorporated
    Inventors: Richard C. Foss, Peter B. Gillingham, Graham Allan
  • Patent number: 6383224
    Abstract: A prosthetic fixing plate comprises a component to be located into the acetabulum prior to the insertion of a prosthetic ball joint cap. The plate has a closure wall adapted to close the wall or rim of the acetabulum across any discontinuity therein, and a locator is provided for locating said closure wall in place. The fixing plate can be supplied in various sizes and arrangements, the correct plate being chosen by the surgeon after close examination of X-ray photographs of the patient and through the use of a template which is used to determine the size and arrangement of the discontinuity and thus the correct size and arrangement of the plate to be used.
    Type: Grant
    Filed: December 16, 1999
    Date of Patent: May 7, 2002
    Assignee: Benoist Girard SAS
    Inventors: Graham Allan Gie, Robin Sydney Mackwood Ling, John Andrew Storer, Andrew John Timperley
  • Publication number: 20020045949
    Abstract: A prosthesis provided with a stem at least part of which is enclosed in a mantle and which is for insertion in a bone cavity and attachment thereto by cement, said mantle having a wall thickness which is increased towards its proximal end to provide an outwardly projecting proximal balcony and which is dimensioned and adapted to locate the stem in a predetermined position within the cross-sectional area of the bone cavity at or towards the proximal end thereof.
    Type: Application
    Filed: September 12, 2001
    Publication date: April 18, 2002
    Inventors: Robin Sydney Mackwood Ling, Graham Allan Gie, Andrew John Timperley, John Andrew Storer
  • Publication number: 20020015460
    Abstract: A delay compensation circuit for a delay locked loop which includes a main delay line having a fine delay line comprising fine delay elements and a coarse delay line comprising coarse delay elements, the main delay line being controlled by a controller, the delay compensation circuit comprising: an adjustable fine delay for modeling a coarse delay element, a counter for controlling the adjustable fine delay to a value which is substantially the same as that of a coarse delay element, a circuit for applying a representation of the system clock to the delay compensation circuit, and a circuit for applying the fine delay count from the counter to the controller for adjusting the fine delay line of the main delay line to a value which is substantially the same as that of a coarse delay element of the main delay line.
    Type: Application
    Filed: October 3, 2001
    Publication date: February 7, 2002
    Inventors: Gurpreet Bhullar, Graham Allan
  • Publication number: 20020007220
    Abstract: A femoral component for a hip replacement joint having a tapered collarless stem for being cemented in a medullary canal. The proximal portion of the stem has a taper and the distal segment is generally circular in cross-section and has a length equal to or greater than the proximal portion. The component can be made in two separate pieces and can be coupled in the metaphysical area of the femur. In one embodiment, at the proximal end of the stem, there is a pronounced laterally projecting heel adapted to extend into the greater trochanter of the femur of the femur into which it is to be filled. Thus, the distal facing part of the heel can provide a lateral portion which is greater than that of known collarless stems and which is particularly adapted to resist torque. In order to fit the femoral component in the medullary canal, it is necessary to broach the medullary canal so that there is a cavity within the greater trochanter.
    Type: Application
    Filed: December 16, 1999
    Publication date: January 17, 2002
    Inventors: GRAHAM ALLAN GIE, ROBIN SYDNEY MACKWOOD LING, JOHN ANDREW STORER, ANDREW JOHN TIMPERLEY
  • Patent number: 6327318
    Abstract: A delay compensation circuit for a delay locked loop which includes a main delay line having a fine delay line comprising fine delay elements and a coarse delay line comprising coarse delay elements, the main delay line being controlled by a controller, the delay compensation circuit comprising: an adjustable fine delay for modeling a coarse delay element, a counter for controlling the adjustable fine delay to a value which is substantially the same as that of a coarse delay element, a circuit for applying a representation of the system clock to the delay compensation circuit, and a circuit for applying the fine delay count from the counter to the controller for adjusting the fine delay line of the main delay line to a value which is substantially the same as that of a coarse delay element of the main delay line.
    Type: Grant
    Filed: June 30, 1998
    Date of Patent: December 4, 2001
    Assignee: Mosaid Technologies Incorporated
    Inventors: Gurpreet Bhullar, Graham Allan
  • Patent number: 6314052
    Abstract: A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.
    Type: Grant
    Filed: January 16, 2001
    Date of Patent: November 6, 2001
    Assignee: Mosaid Technologies Incorporated
    Inventors: Richard C. Foss, Peter B. Gillingham, Graham Allan