Abstract: The invention is suited for use by a hardware designer for the purpose of logic synthesis and/or logic simulation. It can be used in the design of integrated circuits (ASICs) and programmable logic devices (PLDs), such as field-programmable gate arrays (FPGAs). The invention also relates to the field of hardware description languages (HDLs). Embodiments of the invention provide a computer-implemented system and method for facilitating the design of a digital circuit which comprises a plurality of logical constructs. The system is configured such that each time each logical construct is executed during a software simulation pass it is associated with a unique tag, wherein each tag can correspond to a physical aspect of a hardware representation of the design. The simulation is performed by repeated execution passes through code which implements the design, preferably wherein the same tags are associated with corresponding executions of the logical constructs during different simulation passes.

Abstract: The invention is suited for use by a hardware designer for the purpose of logic synthesis and/or logic simulation. It can be used in the design of integrated circuits (ASICs) and programmable logic devices (PLDs), such as field-programmable gate arrays (FPGAs). The invention also relates to the field of hardware description languages (HDLs). Embodiments of the invention provide a computer-implemented system and method for facilitating the design of a digital circuit which comprises a plurality of logical constructs. The system is configured such that each time each logical construct is executed during a software simulation pass it is associated with a unique tag, wherein each tag can correspond to a physical aspect of a hardware representation of the design. The simulation is performed by repeated execution passes through code which implements the design, preferably wherein the same tags are associated with corresponding executions of the logical constructs during different simulation passes.