Abstract: Performance analysis for an electronic system includes determining, using a processor, data traffic patterns stored within a core library of an electronic design automation system, wherein the data traffic patterns are part of cores stored within the core library. The determined data traffic patterns are displayed using a display as modeling options. A user input selecting a displayed data traffic pattern is received; and the selected data traffic pattern is executed as part of modeling the electronic system.

Abstract: Methods and circuits are disclosed for testing a partial circuit design including circuit modules having a set of ports configured to be driven by signals from ports of one or more circuits omitted from the partial circuit. The set of ports are identified by identifying ports that are not connected by a net to another port or input/output (I/O) pin in the circuit design and that form inputs to slave circuits in the circuit modules. A traffic generator circuit is added to the partial design to form a test circuit design. The traffic generator circuit is configured to provide to the set of ports respective input data signals having a pattern consistent with master-to-slave communication. Operation of a test circuit design is modeled. A set of data signals generated by the circuit modules during the modeled operation of the test circuit design is captured and stored.

Abstract: An integrated circuit can include a processor operable to execute program code and an Intellectual Property (IP) modeling block. The IP modeling block can include a first port through which the IP modeling block receives first modeling data and a second port coupled to the processor through which the first IP modeling block communicates with the processor during emulation. The first IP modeling block also can include a power emulation circuit. The power emulation circuit is configured to consume a variable amount of power as specified by the first modeling data received via the first port.

Abstract: A user interface is provided for selection of a previously specified scenario from a plurality of previously specified scenarios. Each previously specified scenario includes a previously specified topology of the electronic system, one or more previously specified parameter values applied to the electronic system, a previously specified traffic profile, and respective precompiled values of one or more measurands. In response to user selection of one of the previously specified scenarios, the precompiled values of the measurands are displayed. The user interface further provides for specification of a scenario. In response to user specification of a scenario, traffic emulation circuitry in the programmable IC is configured to execute the scenario. The value of the at least one measurand is computed and displayed.

Abstract: Pre-boot metadata transfer may include loading a first configuration bitstream into a programmable integrated circuit (IC), wherein the first configuration bitstream includes a first circuit design and metadata for a second circuit design. The metadata may be stored within a memory of the programmable IC. A configuration bitstream load condition may be detected and, responsive to the configuration bitstream load condition, a second configuration bitstream may be loaded into the programmable IC. The second configuration bitstream includes a second circuit design.

Abstract: An integrated circuit (IC) includes a bridge circuit configured to receive a first request from an external system, a discover circuit coupled to the bridge circuit and configured to process the first request received from the bridge circuit, and a memory map coupled to the discover circuit. The memory map stores a record for each of a plurality of Intellectual Property (IP) blocks implemented within the IC. The discover circuit is configured to generate a list of the IP blocks implemented within the IC from the records of the memory map responsive to the first request. The bridge circuit is configured to send the list to the external system.

Abstract: A method of estimating performance of a design can include selecting a segment of the design for hardware emulation within an emulation system implemented within an integrated circuit. The emulation system can include a generic accelerator coupled to a processor of the integrated circuit. The method further can include modifying the design, using a processor of a host system, to invoke the generic accelerator in lieu of executing the selected segment within the processor of the emulation system during emulation.

Abstract: Testing a digital system includes calculating a first ratio of a first clock frequency for a first clock domain and a second clock frequency for a second clock domain different from the first clock domain using a processing device and calculating a first offset between a first timer in the first clock domain and a second timer in the second clock domain. Using an expression dependent upon the first offset and the first ratio, event data from at least one of the first clock domain or the second clock domain is converted to a common clock domain.

Abstract: A method is provided for simulating a processor of network packets. A specification is input for the processor. The specification includes actions specifying a modification of the network packets by the processor. Each action includes a guard condition that enables and disables the action. First and second values of certain fields are determined for each action. The guard condition enables and disables the action respectively for the first and second values of the fields. The network packets are generated. For each field included in the guard conditions, a value of the field is selected for each generated network packet from the values of the field within the first and second values for the actions. The specification of the processor is translated into a simulator of the processor. The modification of the network packets is simulated in the simulator. A result of the modification is displayed on a user interface.

Abstract: A state machine circuit converts a first network packet into a second network packet according to modification actions from a textual language specification. Each modification action is either an insertion action inserting a data segment or a removal action removing a data segment. Each state corresponds to a pairing of a first data word from the first packet and a second data word from the second packet. Each state selects the data units of the second data word from the data segment of each insertion action and the data units of both the first and a prior data word. Each state specifies one or more next states including the state corresponding to the pairing of either the first or a next data word after the first data word in the first sequence and either the second or a next data word after the second data word in the second sequence.

Abstract: A method is provided for generating a hardware description language (HDL) specification of a network packet processor from a textual language specification of the processing of network packets by the processor. The processor includes a look-ahead stage, an operation stage, an insert/remove stage, and an interleave stage. The textual language specification identifies the ports of the processor. The textual language specification includes formats for the type or types of the incoming and outgoing network packets. Each format includes the fields of the type of network packet. The textual language specification includes a procedure for each input port and for each type of incoming network packet received at the input port. Each procedure includes one or more actions for modifying the fields of a type of network packet as a function of state data and/or the fields of the type of network packet.