Patents by Inventor Graham Law
Graham Law has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10985089Abstract: The present invention relates to a semiconductor cooling arrangement for cooling semiconductor devices, such as power semiconductors. The semiconductor cooling arrangement comprises one or more semiconductor assemblies located in a chamber within a housing. The housing comprises inlet and outlet ports for receiving and outputting a cooling medium. The chamber is flooded with a cooling medium to cool the assemblies. The assemblies themselves each comprise a heatsink and one or more semiconductor power devices thermally coupled to the heatsink. The heatsink comprises heat exchanging elements in the form of a plurality of holes in the heatsink extending through the heatsink from one surface to another surface such that the cooling medium flows through the holes to extract heat from the heatsink.Type: GrantFiled: January 30, 2018Date of Patent: April 20, 2021Assignee: YASA LIMITEDInventors: Simon David Hart, Tim Woolmer, Christopher Stuart Malam, Graham Law, Francesca Bernardine Bumpus
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Publication number: 20200006197Abstract: The present invention relates to a semiconductor cooling arrangement for cooling semiconductor devices, such as power semiconductors. The semiconductor cooling arrangement comprises one or more semiconductor assemblies located in a chamber within a housing. The housing comprises inlet and outlet ports for receiving and outputting a cooling medium. The chamber is flooded with a cooling medium to cool the assemblies. The assemblies themselves each comprise a heatsink and one or more semiconductor power devices thermally coupled to the heatsink. The heatsink comprises heat exchanging elements in the form of a plurality of holes in the heatsink extending through the heatsink from one surface to another surface such that the cooling medium flows through the holes to extract heat from the heatsink.Type: ApplicationFiled: January 30, 2018Publication date: January 2, 2020Inventors: Simon David HART, Tim WOOLMER, Christopher Stuart MALAM, Graham LAW, Francesca Bernardine BUMPUS
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Patent number: 8209933Abstract: A connector comprising a guide tube, and a dowel, the guide tube being arranged to receive an end of the dowel, characterized by the end of the dowel passing through the guide tube into a fixing chamber via an orifice, 5 the fixing chamber being arranged to receive a fixing means, the fixing means being arranged to restrict the motion of the dowel within the guide tube.Type: GrantFiled: August 21, 2008Date of Patent: July 3, 2012Assignee: Ancon LimitedInventor: Graham Law
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Publication number: 20100199589Abstract: A connector comprising a guide tube, and a dowel, the guide tube being arranged to receive an end of the dowel, characterised by the end of the dowel passing through the guide tube into a fixing chamber via an orifice, 5 the fixing chamber being arranged to receive a fixing means, the fixing means being arranged to restrict the motion of the dowel within the guide tube.Type: ApplicationFiled: August 21, 2008Publication date: August 12, 2010Inventor: Graham Law
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Patent number: 7038296Abstract: An electrical component structure (14) comprises a plurality of overlying substantially parallel layers (15, 16). Each layer (15, 16) provides a lattice (17, 20) comprising a first set of conductive tracks arranged substantially orthogonal to, and electrically connected with, a second set of conductive tracks. Conductive islands (18, 22) are located in windows of the lattices (17, 20), the conductive islands being electrically isolated from the tracks. The lattice (17, 20) of each layer (15, 16) is electrically connected to the conductive islands (22, 18) of the other adjacent layer (16, 15).Type: GrantFiled: February 6, 2004Date of Patent: May 2, 2006Assignee: Zarlink Semiconductor LimitedInventor: Peter Graham Laws
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Publication number: 20040222494Abstract: An electrical component structure (14) comprises a plurality of overlying substantially parallel layers (15, 16). Each layer (15, 16) provides a lattice (17, 20) comprising a first set of conductive tracks arranged substantially orthogonal to, and electrically connected with, a second set of conductive tracks. Conductive islands (18, 22) are located in windows of the lattices (17, 20), the conductive islands being electrically isolated from the tracks. The lattice (17, 20) of each layer (15, 16) is electrically connected to the conductive islands (22, 18) of the other adjacent layer (16, 15).Type: ApplicationFiled: February 6, 2004Publication date: November 11, 2004Inventor: Peter Graham Laws
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Patent number: 6781482Abstract: An integrated circuit having a substrate and an LC tank circuit comprises an inductor with parallel capacitors. The capacitors include triple plate integrated capacitors having a highest metal plate, a common middle plate and a lowest metal plate. The lowest plate is connected to a virtual ground node. A control circuit element connected to the middle plate allows the resonant frequency of the tank circuit to be controlled.Type: GrantFiled: December 18, 2002Date of Patent: August 24, 2004Assignee: Zarlink Semiconductor LimitedInventor: Peter Graham Laws
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Patent number: 6664824Abstract: A frequency doubler circuit arrangement comprises a full wave rectifier circuit having an input and a first terminal, the first terminal being connected to a first supply terminal via a first current source, and the input forming an input of the frequency doubler circuit arrangement. A biased transistor circuit is also provided, having a first terminal connected to the first supply terminal via a second current source and being connected to the first terminal of the rectifier circuit. Output terminals of the rectifier circuit and the biased transistor circuit form differential output terminals of the frequency doubler circuit arrangement. The respective outputs of the rectifier circuit and the biased transistor circuit may be connected to a second supply terminal via either an active filter load or a passive filter load, such as an inductance-capacitance-resistance filter.Type: GrantFiled: July 24, 2002Date of Patent: December 16, 2003Assignee: Zarlink Semiconductor LimitedInventor: Peter Graham Laws
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Patent number: 6642787Abstract: An amplifier circuit arrangement comprises first and second long-tailed pairs of transistors each including an inductor to provide a constant current source for their respective transistor pair. Each of the transistors of the pairs is provided with a bias current on its base electrode. A differential input signal is applied between the base electrode of one transistor, via a dc blocking capacitor and an input terminal, and the base electrode of another transistor, via a dc blocking capacitor and an another input terminal. The collector electrodes of two of the transistors are connected together and to an output terminal. The collector electrodes of the other two transistors similarly are connected together and to the other output terminal. A differential output signal is provided between the output terminals. This connection of the collectors of the transistors, which can be described as parallel connection, provides summation of the differential signals provided by the transistor pairs.Type: GrantFiled: March 16, 2000Date of Patent: November 4, 2003Assignee: Mitel Semiconductor LimitedInventors: Viatcheslav Igor Souetinov, Peter Graham Laws
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Publication number: 20030142459Abstract: An integrated circuit having a substrate and an LC tank circuit comprises an inductor with parallel capacitors. The capacitors include triple plate integrated capacitors having a highest metal plate, a common middle plate and a lowest metal plate. The lowest plate is connected to a virtual ground node. A control circuit element connected to the middle plate allows the resonant frequency of the tank circuit to be controlled.Type: ApplicationFiled: December 18, 2002Publication date: July 31, 2003Inventor: Peter Graham Laws
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Publication number: 20030025537Abstract: A frequency doubler circuit arrangement comprises a full wave rectifier circuit having an input and a first terminal, the first terminal being connected to a first supply terminal via a first current source, and the input forming an input of the frequency doubler circuit arrangement. A biased transistor circuit is also provided, having a first terminal connected to the first supply terminal via a second current source and being connected to the first terminal of the rectifier circuit. Output terminals of the rectifier circuit and the biased transistor circuit form differential output terminals of the frequency doubler circuit arrangement. The respective outputs of the rectifier circuit and the biased transistor circuit may be connected to a second supply terminal via either an active filter load or a passive filter load, such as an inductance-capacitance-resistance filter.Type: ApplicationFiled: July 24, 2002Publication date: February 6, 2003Applicant: Zarlink Semiconductor LimitedInventor: Peter Graham Laws
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Patent number: 4104714Abstract: A DC to DC converter is provided which may form part of a battery powered gas ignition system, in which the converter comprises a chopper transistor, a transformer having current sensing circuits in the primary and secondary circuits thereof connected in the form of a relaxation oscillator and preferably a supply voltage sensing circuit for effecting a regulation of the battery current in order to obtain substantially maximum power from the battery throughout its useful life.Type: GrantFiled: January 14, 1977Date of Patent: August 1, 1978Assignee: Plessey Handel und Investments AG.Inventors: Richard Hanley Smith, Peter Graham Laws