Abstract: A serial communication system for two IC devices has a separate master chip connected to both of the IC devices, the master chip having a clock generator and circuitry for affecting serial data transmission and control between the master chip and the devices. There is a slave component on each IC device for transforming data between parallel and serial data formats and for sending and receiving a serial data stream. The master chip provides a clock signal to both slave components for gating serial data communication, and manages all communication between the two slave components. In a preferred embodiment all circuitry in the slave components is digital circuitry, and all analog circuitry is implemented on the master chip. Also in a preferred embodiment each slave periodically checks phase between data stream and clock stream received, and inserts a correction code in the data stream sent back to the master chip, so the master chip can regularly correct the phase for clock and data sent to each slave.

Abstract: A serial communication system for two IC devices has a separate master chip connected to both of the IC devices, the master chip having a clock generator and circuitry for affecting serial data transmission and control between the master chip and the devices. There is a slave component on each IC device for transforming data between parallel and serial data formats and for sending and receiving a serial data stream. The master chip provides a clock signal to both slave components for gating serial data communication, and manages all communication between the two slave components. In a preferred embodiment all circuitry in the slave components is digital circuitry, and all analog circuitry is implemented on the master chip. Also in a preferred embodiment each slave periodically checks phase between data stream and clock stream received, and inserts a correction code in the data stream sent back to the master chip, so the master chip can regularly correct the phase for clock and data sent to each slave.

Abstract: A data communication system receives data signals transmitted via a signal path and applies to the received signal a high-pass function including a low-pass filter and a summing circuit. The signal is low-pass filtered, and the summing circuit subtracts the filtered signal from the received signal to generate a high-pass signal, which is summed with a quantized-feedback signal to generate a recovered data signal. The quantized-feedback signal is provided by applying to the recovered data signal a low-pass function having a transfer function which is substantially complementary to the transfer function of the high-pass function. The low-pass function low-pass filters the recovered data signal to generate the quantized-feedback signal.

Abstract: In a line interface circuit for binary data signals means are provided for compensating varying lengths of line in the receiving and/or transmission path. The output signal of a line equalizer controls a variable impedance circuit in such a way that attenuation of a line build out network is reduced if the output level of the line equalizer falls below a threshold. A transmit line build out network provides a frequency dependent attenuation of binary data by means of a control circuit, which supplies discrete attenuation values according to a logic word.