Patents by Inventor Grant Villavicencio
Grant Villavicencio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10806036Abstract: In a method for forming a microelectronic device, a substrate is loaded into a mold press. The substrate has a first surface and a second surface. The second surface is placed on an interior lower surface of the mold press. The substrate has a plurality of wire bond wires extending from the first surface toward an interior upper surface of the mold press. An upper surface of a mold film is indexed to the interior upper surface of the mold press. A lower surface of the mold film is punctured with tips of the plurality of wire bond wires for having the tips of the plurality of wire bond wires extending above the lower surface of the mold film into the mold film. The tips of the plurality of wire bond wires are pressed down toward the lower surface of the mold film to bend the tips over.Type: GrantFiled: January 19, 2018Date of Patent: October 13, 2020Assignee: Invensas CorporationInventors: Reynaldo Co, Grant Villavicencio, Wael Zohni
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Publication number: 20180146557Abstract: In a method for forming a microelectronic device, a substrate is loaded into a mold press. The substrate has a first surface and a second surface. The second surface is placed on an interior lower surface of the mold press. The substrate has a plurality of wire bond wires extending from the first surface toward an interior upper surface of the mold press. An upper surface of a mold film is indexed to the interior upper surface of the mold press. A lower surface of the mold film is punctured with tips of the plurality of wire bond wires for having the tips of the plurality of wire bond wires extending above the lower surface of the mold film into the mold film. The tips of the plurality of wire bond wires are pressed down toward the lower surface of the mold film to bend the tips over.Type: ApplicationFiled: January 19, 2018Publication date: May 24, 2018Applicant: Invensas CorporationInventors: Reynaldo Co, Grant Villavicencio, Wael Zohni
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Patent number: 9888579Abstract: In a method for forming a microelectronic device, a substrate is loaded into a mold press. The substrate has a first surface and a second surface. The second surface is placed on an interior lower surface of the mold press. The substrate has a plurality of wire bond wires extending from the first surface toward an interior upper surface of the mold press. An upper surface of a mold film is indexed to the interior upper surface of the mold press. A lower surface of the mold film is punctured with tips of the plurality of wire bond wires for having the tips of the plurality of wire bond wires extending above the lower surface of the mold film into the mold film. The tips of the plurality of wire bond wires are pressed down toward the lower surface of the mold film to bend the tips over.Type: GrantFiled: March 5, 2015Date of Patent: February 6, 2018Assignee: Invensas CorporationInventors: Reynaldo Co, Grant Villavicencio, Wael Zohni
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Patent number: 9659848Abstract: A component can include a generally planar element, a reinforcing dielectric layer overlying the generally planar element, an encapsulation overlying the reinforcing dielectric layer, and a plurality of wire bonds. Each wire bond can have a tip at a major surface of the encapsulation. The wire bonds can have first portions extending within the reinforcing dielectric layer. The first portions of at least some of the wire bonds can have bends that change an extension direction of the respective wire bond. The reinforcing dielectric layer can have protruding regions surrounding respective ones of the wire bonds, the protruding regions extending to greater peak heights from the first surface of the generally planar element than portions of the reinforcing dielectric layer between adjacent ones of the protruding regions. The peak heights of the protruding regions can coincide with points of contact between the reinforcing dielectric layer and individual wire bonds.Type: GrantFiled: March 31, 2016Date of Patent: May 23, 2017Assignee: Invensas CorporationInventors: Grant Villavicencio, Sangil Lee, Roseann Alatorre, Javier A. Delacruz, Scott McGrath
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Publication number: 20170141020Abstract: A component can include a generally planar element, a reinforcing dielectric layer overlying the generally planar element, an encapsulation overlying the reinforcing dielectric layer, and a plurality of wire bonds. Each wire bond can have a tip at a major surface of the encapsulation. The wire bonds can have first portions extending within the reinforcing dielectric layer. The first portions of at least some of the wire bonds can have bends that change an extension direction of the respective wire bond. The reinforcing dielectric layer can have protruding regions surrounding respective ones of the wire bonds, the protruding regions extending to greater peak heights from the first surface of the generally planar element than portions of the reinforcing dielectric layer between adjacent ones of the protruding regions. The peak heights of the protruding regions can coincide with points of contact between the reinforcing dielectric layer and individual wire bonds.Type: ApplicationFiled: March 31, 2016Publication date: May 18, 2017Inventors: Grant Villavicencio, Sangil Lee, Roseann Alatorre, Javier A. Delacruz, Scott McGrath
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Patent number: 9508689Abstract: Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.Type: GrantFiled: September 30, 2015Date of Patent: November 29, 2016Assignee: Invensas CorporationInventors: Reynaldo Co, Jeffrey S. Leal, Suzette K. Pangrle, Scott McGrath, De Ann Eileen Melcher, Keith L. Barrie, Grant Villavicencio, Elmer M. Del Rosario, John R. Bray
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Publication number: 20160262268Abstract: In a method for forming a microelectronic device, a substrate is loaded into a mold press. The substrate has a first surface and a second surface. The second surface is placed on an interior lower surface of the mold press. The substrate has a plurality of wire bond wires extending from the first surface toward an interior upper surface of the mold press. An upper surface of a mold film is indexed to the interior upper surface of the mold press. A lower surface of the mold film is punctured with tips of the plurality of wire bond wires for having the tips of the plurality of wire bond wires extending above the lower surface of the mold film into the mold film. The tips of the plurality of wire bond wires are pressed down toward the lower surface of the mold film to bend the tips over.Type: ApplicationFiled: March 5, 2015Publication date: September 8, 2016Applicant: INVENSAS CORPORATIONInventors: Reynaldo CO, Grant VILLAVICENCIO, Wael ZOHNI
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Publication number: 20160027761Abstract: Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.Type: ApplicationFiled: September 30, 2015Publication date: January 28, 2016Applicant: INVENSAS CORPORATIONInventors: Reynaldo Co, Jeffrey S. Leal, Suzette K. Pangrle, Scott McGrath, De Ann Eileen Melcher, Keith L. Barrie, Grant Villavicencio, Elmer M. Del Rosario, John R. Bray
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Patent number: 9153517Abstract: Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.Type: GrantFiled: May 17, 2011Date of Patent: October 6, 2015Assignee: Invensas CorporationInventors: Reynaldo Co, Jeffrey S. Leal, Suzette K. Pangrle, Scott McGrath, DeAnn Eileen Melcher, Keith L. Barrie, Grant Villavicencio, Elmer M. del Rosario, John R. Bray
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Publication number: 20150056753Abstract: A die has interconnect pads on an interconnect side near an interconnect edge and has at least a portion of the interconnect side covered by a conformal dielectric coating, in which an interconnect trace over the dielectric coating forms a high interface angle with the surface of the dielectric coating. Because the traces have a high interface angle, a tendency for the interconnect materials to “bleed” laterally is mitigated and contact or overlap of adjacent traces is avoided. The interconnect trace includes a curable electrically conductive interconnect material; that is, it includes a material that can be applied in a flowable form, and thereafter cured or allowed to cure to form the conductive traces. Also, a method includes, prior to forming the traces, subjecting the surface of the conformal dielectric coating with a CF4 plasma treatment.Type: ApplicationFiled: September 8, 2014Publication date: February 26, 2015Applicant: INVENSAS CORPORATIONInventors: Keith Lake Barrie, Suzette K. Pangrle, Grant Villavicencio, Jeffrey S. Leal
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Patent number: 8884403Abstract: According to the invention, die shift is reduced or substantially eliminated, by cutting the wafer in two stages. In some embodiments a first wafer cutting procedure is carried out prior to thinning the wafer to the prescribed die thickness; and in other embodiments the wafer is thinned to the prescribed die thickness prior to carrying out a first wafer cutting procedure. The first wafer cutting procedure includes cutting along a first set of streets to a depth greater than the prescribed die thickness and optionally along a second set of streets to a depth less than the die thickness. The result of the first cutting procedure is an array of strips or blocks of die, each including a plurality of connected die, that are less subject to shift than are individual singulated die. In a second wafer cutting procedure the die are singulated by cutting through along the second set of streets.Type: GrantFiled: December 30, 2010Date of Patent: November 11, 2014Assignee: Iinvensas CorporationInventors: Reynaldo Co, DeAnn Eileen Melcher, Weiping Pan, Grant Villavicencio
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Patent number: 8829677Abstract: A die has interconnect pads on an interconnect side near an interconnect edge and has at least a portion of the interconnect side covered by a conformal dielectric coating, in which an interconnect trace over the dielectric coating forms a high interface angle with the surface of the dielectric coating. Because the traces have a high interface angle, a tendency for the interconnect materials to “bleed” laterally is mitigated and contact or overlap of adjacent traces is avoided. The interconnect trace includes a curable electrically conductive interconnect material; that is, it includes a material that can be applied in a flowable form, and thereafter cured or allowed to cure to form the conductive traces. Also, a method includes, prior to forming the traces, subjecting the surface of the conformal dielectric coating with a CF4 plasma treatment.Type: GrantFiled: September 23, 2011Date of Patent: September 9, 2014Assignee: Invensas CorporationInventors: Keith Lake Barrie, Suzette K. Pangrie, Grant Villavicencio, Jeffrey S. Leal
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Patent number: 8680687Abstract: A die (or of a stack of die) is mounted over and elevated above a support, and is electrically connected to circuitry in the support. Pillars of electrically conductive material are formed on a set of bond pads at a mount side of the support, and the elevated die (or at least one die in the elevated stack of die) is electrically connected to the support, by traces of an electrically conductive material contacting interconnect pads on the die to the pillars, and through the pillars to the support. Also, tiered offset stacked die assemblies in a zig-zag configuration, in which the interconnect edges of a first (lower) tier face in a first direction, and the interconnect edges of a second (upper) tier, stacked over the first tier, face in a second direction, different from the first direction, are electrically connected to a support.Type: GrantFiled: June 23, 2010Date of Patent: March 25, 2014Assignee: Invensas CorporationInventors: Reynaldo Co, Grant Villavicencio, Jeffrey S. Leal, Simon J. S. McElrea
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Patent number: 8324081Abstract: An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board).Type: GrantFiled: March 4, 2011Date of Patent: December 4, 2012Inventors: Simon J. S. McElrea, Terrence Caskey, Scott McGrath, DeAnn Eileen Melcher, Reynaldo Co, Lawrence Douglas Andrews, Jr., Weiping Pan, Grant Villavicencio, Yong Du, Scott Jay Crane, Zongrong Liu
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Publication number: 20120248607Abstract: A die has interconnect pads on an interconnect side near an interconnect edge and has at least a portion of the interconnect side covered by a conformal dielectric coating, in which an interconnect trace over the dielectric coating forms a high interface angle with the surface of the dielectric coating. Because the traces have a high interface angle, a tendency for the interconnect materials to “bleed” laterally is mitigated and contact or overlap of adjacent traces is avoided. The interconnect trace includes a curable electrically conductive interconnect material; that is, it includes a material that can be applied in a flowable form, and thereafter cured or allowed to cure to form the conductive traces. Also, a method includes, prior to forming the traces, subjecting the surface of the conformal dielectric coating with a CF4 plasma treatment.Type: ApplicationFiled: September 23, 2011Publication date: October 4, 2012Applicant: VERTICAL CIRCUITS, INC.Inventors: Keith Lake Barrie, Suzette K. Pangrle, Grant Villavicencio, Jeffrey S. Leal
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Publication number: 20120119385Abstract: Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.Type: ApplicationFiled: May 17, 2011Publication date: May 17, 2012Applicant: VERTICAL CIRCUITS, INC.Inventors: Reynaldo Co, Jeffrey S. Leal, Suzette K. Pangrle, Scott McGrath, DeAnn Elleen Melcher, Keith L. Barrie, Grant Villavicencio, Elmer M. del Rosario, John R. Bray
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Publication number: 20110147943Abstract: An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board).Type: ApplicationFiled: March 4, 2011Publication date: June 23, 2011Applicant: Vertical Circuits, Inc.Inventors: Simon J. S. McElrea, Terrence Caskey, Scott McGrath, DeAnn Eileen Melcher, Reynaldo Co, Lawrence Douglas Andrews, JR., Weiping Pan, Grant Villavicencio, Yong Du, Scott Jay Crane, Zongrong Liu
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Publication number: 20110101505Abstract: According to the invention, die shift is reduced or substantially eliminated, by cutting the wafer in two stages. In some embodiments a first wafer cutting procedure is carried out prior to thinning the wafer to the prescribed die thickness; and in other embodiments the wafer is thinned to the prescribed die thickness prior to carrying out a first wafer cutting procedure. The first wafer cutting procedure includes cutting along a first set of streets to a depth greater than the prescribed die thickness and optionally along a second set of streets to a depth less than the die thickness. The result of the first cutting procedure is an array of strips or blocks of die, each including a plurality of connected die, that are less subject to shift than are individual singulated die. In a second wafer cutting procedure the die are singulated by cutting through along the second set of streets.Type: ApplicationFiled: December 30, 2010Publication date: May 5, 2011Applicant: Vertical Circuits, Inc.Inventors: Reynaldo Co, DeAnn Eileen Melcher, Weiping Pan, Grant Villavicencio
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Patent number: 7923349Abstract: An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board).Type: GrantFiled: June 19, 2008Date of Patent: April 12, 2011Assignee: Vertical Circuits, Inc.Inventors: Simon J. S. McElrea, Terrence Caskey, Scott McGrath, DeAnn Eileen Melcher, Reynaldo Co, Lawrence Douglas Andrews, Jr., Weiping Pan, Grant Villavicencio, Yong Du, Scott Jay Crane, Zongrong Liu
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Patent number: 7863159Abstract: According to the invention, die shift is reduced or substantially eliminated, by cutting the wafer in two stages. In some embodiments a first wafer cutting procedure is carried out prior to thinning the wafer to the prescribed die thickness; and in other embodiments the wafer is thinned to the prescribed die thickness prior to carrying out a first wafer cutting procedure. The first wafer cutting procedure includes cutting along a first set of streets to a depth greater than the prescribed die thickness and optionally along a second set of streets to a depth less than the die thickness. The result of the first cutting procedure is an array of strips or blocks of die, each including a plurality of connected die, that are less subject to shift than are individual singulated die. In a second wafer cutting procedure the die are singulated by cutting through along the second set of streets.Type: GrantFiled: November 25, 2008Date of Patent: January 4, 2011Assignee: Vertical Circuits, Inc.Inventors: Reynaldo Co, DeAnn Eileen Melcher, Weiping Pan, Grant Villavicencio