Patents by Inventor Grant Wagner
Grant Wagner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11675010Abstract: Aspects of the invention include a wafer test device with a conformal laminate and rigid probes extending from the laminate to form an electrical connection with a microcircuit under test. The wafer test device also includes a spring plate on a side of the laminate that is opposite a side from which the rigid probes extend. The spring plate includes a conformal inner frame and a rigid outer frame. The laminate is attached to the inner frame of the spring plate.Type: GrantFiled: November 30, 2021Date of Patent: June 13, 2023Assignee: International Business Machines CorporationInventors: David Michael Audette, Grant Wagner, Jacob Louis Moore, Peter William Neff
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Publication number: 20230168301Abstract: Aspects of the invention include a wafer test device with a conformal laminate and rigid probes extending from the laminate to form an electrical connection with a microcircuit under test. The wafer test device also includes a spring plate on a side of the laminate that is opposite a side from which the rigid probes extend. The spring plate includes a conformal inner frame and a rigid outer frame. The laminate is attached to the inner frame of the spring plate.Type: ApplicationFiled: November 30, 2021Publication date: June 1, 2023Inventors: David Michael Audette, Grant Wagner, Jacob Louis Moore, Peter William Neff
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Patent number: 11662366Abstract: A wafer test device includes a test interconnect to interface with a microcircuit of the wafer at a first side and an interposer to interface with the test interconnect at a second side of the test interconnect, opposite the first side. The interposer connects the test interconnect, via a printed circuit board (PCB), to a test apparatus that determines and controls test patterns that are applied to the microcircuit via the test interconnect. A support structure supports the test interconnect and the interposer. The support structure includes an inner bearing to tilt the test interconnect to match a tilt of a surface of the microcircuit. An elastomer between the test interconnect and the interposer reduces deflection of the test interconnect during a process of connecting the test interconnect to the microcircuit.Type: GrantFiled: September 21, 2021Date of Patent: May 30, 2023Assignee: International Business Machines CorporationInventors: David Michael Audette, Grant Wagner, Jacob Louis Moore, Peter William Neff
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Publication number: 20230089411Abstract: A wafer test device includes a test interconnect to interface with a microcircuit of the wafer at a first side and an interposer to interface with the test interconnect at a second side of the test interconnect, opposite the first side. The interposer connects the test interconnect, via a printed circuit board (PCB), to a test apparatus that determines and controls test patterns that are applied to the microcircuit via the test interconnect. A support structure supports the test interconnect and the interposer. The support structure includes an inner bearing to tilt the test interconnect to match a tilt of a surface of the microcircuit. An elastomer between the test interconnect and the interposer reduces deflection of the test interconnect during a process of connecting the test interconnect to the microcircuit.Type: ApplicationFiled: September 21, 2021Publication date: March 23, 2023Inventors: David Michael Audette, Grant Wagner, Jacob Louis Moore, Peter William Neff
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Patent number: 11561243Abstract: A wafer test device and methods of assembling a wafer test device involve a first laminate structure, and a second laminate structure arranged to interface with a microcircuit of the wafer. The wafer test device includes a compliant layer between the first laminate structure and the second laminate structure. The compliant layer includes an elastomer that exhibits compliance within a limited range of movement.Type: GrantFiled: September 12, 2019Date of Patent: January 24, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Audette, Grant Wagner, Marc Knox, Dennis Conti
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Patent number: 11322473Abstract: Aspects of the invention include a method of tuning an interconnect that couples a first structure that is a first integrated circuit or a first laminate structure to a second structure that is a second integrated circuit or a second laminate structure. The method includes obtaining a compression requirement for a spring in a compliant layer of the interconnect. A longer path length of the spring leads to greater compression and mechanical support. Current and signal speed requirements for the interconnect are obtained. A shorter path length of the spring leads to greater current-carrying capacity and greater signal speed. Specifications for the spring are determined based on the compression requirement and the current and signal speed requirements. Determining the specifications includes determining a number of active coils of the spring to be less than two.Type: GrantFiled: September 12, 2019Date of Patent: May 3, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Audette, Grant Wagner, Marc Knox, Dennis Conti
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Patent number: 11131689Abstract: Embodiments herein describe structures of low-force wafer test probes and formation thereof. Structures of low-force wafer test probes and their formation via gray scale etch or electroplating is described. Structures are described that include a lower base structure on top of a substrate and an upper blade structure on top of the lower base structure. In various embodiments, a crown of a C4 bump is accommodated by one or both of: i) a cavity present in the lower base structure; and ii) a height of the upper blade structure. Processes for fabricating probe structures are described that include forming lower base structures upon a substrate and forming upper blade structures on top of the lower base structures. The upper blade structures include at least one blade. Each of the blade(s) include a cutting edge that points toward a center point within the probe structure.Type: GrantFiled: May 25, 2017Date of Patent: September 28, 2021Assignee: International Business Machines CorporationInventors: David M. Audette, S J. Chey, Doreen D. DiMilia, Sankeerth Rajalingam, Grant Wagner
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Patent number: 11041879Abstract: A semiconductor die is aligned to a test probe by placing the semiconductor die onto a flat upper surface of a test stage with solder balls of the die facing upward, fluidizing motion of the die with reference to the test stage by pulsing gas between the die and the upper surface of the test stage, and coarse aligning the die with reference to the test stage by moving the die until adjacent edges of the die contact corner guides that are disposed on the test stage. Further, the method includes raising the test stage toward the test probe until an alignment feature of the test probe engages a first solder ball of the die, and fine aligning the die with reference to the test probe by continuing to raise the test stage until a second solder ball of the die fits into a test cup of the test probe.Type: GrantFiled: June 6, 2019Date of Patent: June 22, 2021Assignee: International Business Machines CorporationInventors: Eugene Atwood, David Audette, Grant Wagner
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Patent number: 11009545Abstract: An integrated circuit (IC) device tester includes contact probes. A liner is formed upon the contact probes. The liner includes a matrix of metal particles and glass particles. The metal particles of the liner allow the contact probe to pass an electrical current through the liner. The glass particles of the liner prevent C4 material from adhering to the liner.Type: GrantFiled: March 12, 2020Date of Patent: May 18, 2021Assignee: International Business Machines CorporationInventors: Charles L. Arvin, David M. Audette, Dennis R. Conti, Brian M. Erwin, Grant Wagner
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Patent number: 10955439Abstract: A method of treating a material on a probe is provided. The method includes the steps of immersing a probe tip into a first fluid, wherein the probe tip includes one or more oxidized metallic fragments on a surface of the probe tip; polarizing the probe tip, through a counter electrode, with a negative current to reduce the one or more oxidized metallic fragments to one or more substantially unoxidized metallic fragments; removing the probe tip from the first fluid; immersing the probe in a second fluid, wherein the second fluid is a complexer for the one or more substantially unoxidized metallic fragments; and polarizing the probe tip with a positive current, through the counter electrode, wherein the positive current oxidizes the one or more substantially unoxidized metallic fragments.Type: GrantFiled: March 12, 2019Date of Patent: March 23, 2021Assignee: International Business Machines CorporationInventors: Charles L. Arvin, David M. Audette, Grant Wagner
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Publication number: 20210080486Abstract: A wafer test device and methods of assembling a wafer test device involve a first laminate structure, and a second laminate structure arranged to interface with a microcircuit of the wafer. The wafer test device includes a compliant layer between the first laminate structure and the second laminate structure. The compliant layer includes an elastomer that exhibits compliance within a limited range of movement.Type: ApplicationFiled: September 12, 2019Publication date: March 18, 2021Inventors: David Audette, Grant Wagner, Marc Knox, Dennis Conti
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Publication number: 20210082860Abstract: Aspects of the invention include a method of tuning an interconnect that couples a first structure that is a first integrated circuit or a first laminate structure to a second structure that is a second integrated circuit or a second laminate structure. The method includes obtaining a compression requirement for a spring in a compliant layer of the interconnect. A longer path length of the spring leads to greater compression and mechanical support. Current and signal speed requirements for the interconnect are obtained. A shorter path length of the spring leads to greater current-carrying capacity and greater signal speed. Specifications for the spring are determined based on the compression requirement and the current and signal speed requirements. Determining the specifications includes determining a number of active coils of the spring to be less than two.Type: ApplicationFiled: September 12, 2019Publication date: March 18, 2021Inventors: David Audette, Grant Wagner, Marc Knox, Dennis Conti
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Publication number: 20200386785Abstract: A semiconductor die is aligned to a test probe by placing the semiconductor die onto a flat upper surface of a test stage with solder balls of the die facing upward, fluidizing motion of the die with reference to the test stage by pulsing gas between the die and the upper surface of the test stage, and coarse aligning the die with reference to the test stage by moving the die until adjacent edges of the die contact corner guides that are disposed on the test stage.Type: ApplicationFiled: June 6, 2019Publication date: December 10, 2020Inventors: Eugene Atwood, David Audette, Grant Wagner
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Publication number: 20200292577Abstract: A method of treating a material on a probe is provided. The method includes the steps of immersing a probe tip into a first fluid, wherein the probe tip includes one or more oxidized metallic fragments on a surface of the probe tip; polarizing the probe tip, through a counter electrode, with a negative current to reduce the one or more oxidized metallic fragments to one or more substantially unoxidized metallic fragments; removing the probe tip from the first fluid; immersing the probe in a second fluid, wherein the second fluid is a complexer for the one or more substantially unoxidized metallic fragments; and polarizing the probe tip with a positive current, through the counter electrode, wherein the positive current oxidizes the one or more substantially unoxidized metallic fragments.Type: ApplicationFiled: March 12, 2019Publication date: September 17, 2020Inventors: Charles L. Arvin, David M. Audette, Grant Wagner
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Publication number: 20200209308Abstract: An integrated circuit (IC) device tester includes contact probes. A liner is formed upon the contact probes. The liner includes a matrix of metal particles and glass particles. The metal particles of the liner allow the contact probe to pass an electrical current through the liner. The glass particles of the liner prevent C4 material from adhering to the liner.Type: ApplicationFiled: March 12, 2020Publication date: July 2, 2020Inventors: Charles L. Arvin, David M. Audette, Dennis R. Conti, Brian M. Erwin, Grant Wagner
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Patent number: 10670653Abstract: An integrated circuit (IC) device tester includes contact probes. A liner is formed upon the contact probes. The liner includes a matrix of an electrical conductor and glass. The conductor of the liner provides for the contact probe to be electrically connected to the IC device contact. The glass of the liner prevents IC device contact material adhering thereto. The liner may be formed by applying a conductive glass frit upon a probe card that includes the probe contacts and locally thermally conditioning the conductive glass frit upon contact probes. By locally thermally conditioning the conductive glass frit, the temperature of the probe card may be maintained below a critical temperature that damages the probe card.Type: GrantFiled: May 15, 2018Date of Patent: June 2, 2020Assignee: International Business Machines CorporationInventors: Charles L. Arvin, David M. Audette, Dennis R. Conti, Brian M. Erwin, Grant Wagner
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Publication number: 20190353702Abstract: An integrated circuit (IC) device tester includes contact probes. A liner is formed upon the contact probes. The liner includes a matrix of an electrical conductor and glass. The conductor of the liner provides for the contact probe to be electrically connected to the IC device contact. The glass of the liner prevents IC device contact material adhering thereto. The liner may be formed by applying a conductive glass frit upon a probe card that includes the probe contacts and locally thermally conditioning the conductive glass frit upon contact probes. By locally thermally conditioning the conductive glass frit, the temperature of the probe card may be maintained below a critical temperature that damages the probe card.Type: ApplicationFiled: May 15, 2018Publication date: November 21, 2019Inventors: Charles L. Arvin, David M. Audette, Dennis R. Conti, Brian M. Erwin, Grant Wagner
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Publication number: 20190227100Abstract: Embodiments herein describe structures of low-force wafer test probes and formation thereof. Structures of low-force wafer test probes and their formation via gray scale etch or electroplating is described. Structures are described that include a lower base structure on top of a substrate and an upper blade structure on top of the lower base structure. In various embodiments, a crown of a C4 bump is accommodated by one or both of: i) a cavity present in the lower base structure; and ii) a height of the upper blade structure. Processes for fabricating probe structures are described that include forming lower base structures upon a substrate and forming upper blade structures on top of the lower base structures. The upper blade structures include at least one blade. Each of the blade(s) include a cutting edge that points toward a center point within the probe structure.Type: ApplicationFiled: April 2, 2019Publication date: July 25, 2019Inventors: David M. Audette, S J. Chey, Doreen D. DiMilia, Sankeerth Rajalingam, Grant Wagner
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Publication number: 20180358322Abstract: A method of pressing solder bumps using a pressing apparatus before testing a wafer, including loading the wafer into the pressing apparatus, where the wafer includes a number of chips, and the wafer is aligned with respect to a test head of the pressing apparatus. The test head includes a substrate which has pressing structures arranged across a surface of the substrate facing the wafer. The pressing structures contact the solder bumps, where the solder bumps include a first surface topology and the pressing structures include a pressing surface topology prior to the contact. The caused contact includes altering a shape of each of the plurality of solder bumps, such that the plurality of solder bumps then a second surface topology after the caused contact, and the second surface topology of the solder bumps matches the pressing surface topology after the caused contact.Type: ApplicationFiled: December 19, 2017Publication date: December 13, 2018Inventors: David M. Audette, Sukjay Chey, Dennis R. Conti, Marc D. Knox, Sankeerth Rajalingam, Cedric Speltz, Grant Wagner
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Publication number: 20180358321Abstract: A method of pressing solder bumps using a pressing apparatus before testing a wafer, including loading the wafer into the pressing apparatus, where the wafer includes a number of chips, and the wafer is aligned with respect to a test head of the pressing apparatus. The test head includes a substrate which has pressing structures arranged across a surface of the substrate facing the wafer. The pressing structures contact the solder bumps, where the solder bumps include a first surface topology and the pressing structures include a pressing surface topology prior to the contact. The caused contact includes altering a shape of each of the plurality of solder bumps, such that the plurality of solder bumps then a second surface topology after the caused contact, and the second surface topology of the solder bumps matches the pressing surface topology after the caused contact.Type: ApplicationFiled: June 13, 2017Publication date: December 13, 2018Inventors: David M. Audette, Sukjay Chey, Dennis R. Conti, Marc D. Knox, Sankeerth Rajalingam, Cedric Speltz, Grant Wagner