Abstract: A device includes a memory. The device also includes a controller. The controller includes a register configured to store an indication of whether an ability of a received command to alter an access protection scheme of the memory is enabled. The received command may alter the access an access protection scheme of the memory responsive to the indication.

Abstract: Methods and apparatuses are disclosed for executing a plurality of queued tasks in a memory. One example apparatus includes a memory configured to be coupled to a host. The memory is also configured to receive a plurality of memory access requests, a status request, and an execution command from the host, and to execute one or more of the plurality of memory access requests responsive to the execution command from the host. The execution command includes a plurality of respective indications that correspond to each respective memory access request of the plurality of memory access requests and that indicate whether the host is requesting the memory to execute each respective memory access request.

Abstract: Methods, systems, and devices for architecture-based power management for a memory device are described. Aspects include operating a first memory bank within a memory device in a first mode and a second memory bank within the memory device in a second mode. The memory device may receive a power down command for the first memory bank while operating the first memory bank in the first mode and the second memory bank in the second mode and switch the first memory bank from the first mode to a first low power mode while maintaining the second memory bank in the second mode. The first low power mode corresponds to less power consumption by the first memory bank than the first mode. In some cases, switching the first memory bank from the first mode to the first low power mode includes deactivating circuitry dedicated to the first memory bank.

Abstract: Methods, systems, and devices for bank-configurable power modes are described. Aspects include operating a memory device that has multiple memory banks in a first mode. While operating in the first mode, the memory device may receive a command to enter a second mode having a lower power consumption level than the first mode. The memory device may enter the second mode by switching a first subset of the memory banks to a first low power mode that operates at a first power consumption level and a second subset of the memory banks to a second low power mode that operates at a second power consumption level that may be lower than the first power consumption level. In some cases, the memory device may switch the first subset of memory banks from the first low power mode while maintaining the second subset of memory banks in the low power mode.

Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a certain number bits having a first logic state prior to storing the user data in memory cells. Subsequently, reading the encoded user data may be carried out by applying a read voltage to the memory cells while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. The auto-referenced read may identify a particular switching event that correlates to a median threshold voltage value of the subset of the memory cells. Then, the auto-referenced read may determine a reference voltage that takes into account a statistical property of threshold voltage distribution of the subset of the memory cells. The auto-referenced read may identify a time duration to maintain the read voltage based on determining the reference voltage.

Abstract: Apparatuses and methods for performing memory operations are described. An example apparatus includes a memory operation controller. The memory operation controller is configured to receive memory instructions and decode the same to provide internal signals for performing memory operations for the memory instructions. The memory operation controller is further configured to provide information indicative of a time for a variable latency period of a memory instruction during the variable latency period. In an example method, a write instruction and an address to which write data is to be written is received at a memory and an acknowledgement indicative of an end of a variable latency period for the write instruction is provided. After waiting a variable bus turnaround after the acknowledgement, write data for the write instruction is received.

Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a predetermined number of bits having a first logic state prior to storing the user data in memory cells. The auto-referenced read may store a total number of bits of the user data having a first logic state in a separate set of memory cells. Subsequently, reading the user data may be carried out by applying a read voltage to the memory cells storing the user data while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. During the read operation, the auto-referenced read may compare the number of activated memory cells to either the predetermined number or the total number to determine whether all the bits having the first logic state has been detected.

Abstract: Techniques herein may allow a row of a subarray in a bank of a memory device to be activated before a precharge operation has been completed for a previously opened row of memory cells in the same bank. Each subarray within the bank may be associated with a respective local latching circuit, which may be used to maintain phases at the subarray independent of subsequent commands to the same bank. For example, the latching circuit may internalize timing signals triggered by a precharge command for a first row such that if an activation command is received for a different subarray in the same bank at a time before the precharge operation of the first row is complete, the precharge operation may continue until the first row is closed, as the timing signals triggered by the precharge command may be maintained locally at the subarray using the latching circuit.

Abstract: The present disclosure includes apparatuses and methods for providing power availability information to memory. A number of embodiments include a memory and a controller. The controller is configured to provide power and power availability information to the memory, and the memory is configured to determine whether to adjust its operation based, at least in part, on the power availability information.

Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a predetermined number of bits having a first logic state prior to storing the user data in memory cells. The auto-referenced read may store a total number of bits of the user data having a first logic state in a separate set of memory cells. Subsequently, reading the user data may be carried out by applying a read voltage to the memory cells storing the user data while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. During the read operation, the auto-referenced read may compare the number of activated memory cells to either the predetermined number or the total number to determine whether all the bits having the first logic state has been detected.

Abstract: Devices and techniques for storage class memory status are disclosed herein. A storage portion characteristics data structure is maintained. Here, the data structure includes an array of elements—where each element is sized to contain a reference to a storage portion in a storage class memory storage device, a first pointer to a first element in the array of elements, a second pointer to a second element in the array of elements, and a third pointer to a third element in the array of elements. The data structure includes a direction of pointer motion in which the second pointer precedes the third pointer and the first pointer precedes the second pointer with respect to the direction of pointer motion. A write request is performed to a storage portion reference retrieved from the first element. The first pointer is then advanced.

Abstract: Apparatuses and methods for performing memory operations are described. In an example apparatus, a memory is configured to receive a memory instruction and perform a memory operation responsive to the memory instruction. The memory is further configured to provide an acknowledgement indicative of an end of the variable latency period wherein the acknowledgement includes information related to an acceptance of a memory instruction. Data associated with the memory instruction is exchanged with the memory following the acknowledgement. In an example method a read instruction and an address from which read data is to be read is received. A write operation is suspended responsive to the read instruction and an acknowledgement indicative of an end of the variable latency period is provided. Read data for the read instruction is provided and the write operation is continued to be suspended for a hold-off period following completion of the read operation.

Abstract: Systems and methods for vendor-agnostic access to non-volatile memory of a wireless memory tag are provided. A wireless memory host includes a radio and controller. The controller generates vendor-agnostic commands to access a register-based interface that ultimately results in access to the non-volatile memory.

Abstract: Apparatuses and methods for providing data to a configurable storage area are described herein. An example apparatus may include an extended address register including a plurality of configuration bits indicative of an offset and a size, an array having a storage area, a size and offset of the storage area based, at least in part, on the plurality of configuration bits, and a buffer configured to store data, the data including data intended to be stored in the storage area. A memory control unit may be coupled to the buffer and configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command.

Abstract: Apparatuses and methods related to providing transaction metadata. Providing transaction metadata includes providing an address of data stored in the memory device using an address bus coupled to the memory device and the controller. Providing transaction metadata also includes transferring the data, associated with the address, from the memory device using a data bus coupled to the memory device and the controller. Providing transaction metadata further includes transferring a sideband signal synchronously with the data bus and in conjunction with the address bus using a transaction metadata bus coupled to the memory device and the controller.

Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a certain number bits having a first logic state prior to storing the user data in memory cells. Subsequently, reading the encoded user data may be carried out by applying a read voltage to the memory cells while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. The auto-referenced read may identify a particular switching event that correlates to a median threshold voltage value of the subset of the memory cells. Then, the auto-referenced read may determine a reference voltage that takes into account a statistical property of threshold voltage distribution of the subset of the memory cells. The auto-referenced read may identify a time duration to maintain the read voltage based on determining the reference voltage.

Abstract: The present disclosure includes apparatuses and methods for providing power availability information to memory. A number of embodiments include a memory and a controller. The controller is configured to provide power and power availability information to the memory, and the memory is configured to determine whether to adjust its operation based, at least in part, on the power availability information.

Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a predetermined number of bits having a first logic state prior to storing the user data in memory cells. The auto-referenced read may store a total number of bits of the user data having a first logic state in a separate set of memory cells. Subsequently, reading the user data may be carried out by applying a read voltage to the memory cells storing the user data while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. During the read operation, the auto-referenced read may compare the number of activated memory cells to either the predetermined number or the total number to determine whether all the bits having the first logic state has been detected.

Abstract: Systems and methods for vendor-agnostic access to non-volatile memory of a wireless memory tag include: detecting, via a wireless memory host, a wireless memory tag; providing a vendor-agnostic command to the wireless memory tag to affect a change in a register-based interface of the wireless memory tag, wherein the change results in reading data from non-volatile memory of the wireless memory tag, writing data to the non-volatile memory of the wireless memory tag, or both.

Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a certain number bits having a first logic state prior to storing the user data in memory cells. Subsequently, reading the encoded user data may be carried out by applying a read voltage to the memory cells while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. The auto-referenced read may identify a particular switching event that correlates to a median threshold voltage value of the subset of the memory cells. Then, the auto-referenced read may determine a reference voltage that takes into account a statistical property of threshold voltage distribution of the subset of the memory cells. The auto-referenced read may identify a time duration to maintain the read voltage based on determining the reference voltage.