Patents by Inventor Greg Regnier
Greg Regnier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11063884Abstract: This disclosure describes enhancements to Ethernet for use in higher performance applications like Storage, HPC, and Ethernet based fabric interconnects. This disclosure provides various mechanisms for lossless fabric enhancements with error-detection and retransmissions to improve link reliability, frame pre-emption to allow higher priority traffic over lower priority traffic, virtual channel support for deadlock avoidance by enhancing Class of service functionality defined in IEEE 802.1Q, a new header format for efficient forwarding/routing in the fabric interconnect and header CRC for reliable cut-through forwarding in the fabric interconnect. The enhancements described herein, when added to standard and/or proprietary Ethernet protocols, broadens the applicability of Ethernet to newer usage models and fabric interconnects that are currently served by alternate fabric technologies like Infiniband, Fibre Channel and/or other proprietary technologies, etc.Type: GrantFiled: August 28, 2019Date of Patent: July 13, 2021Assignee: Intel CorporationInventors: Ilango Ganga, Alain Gravel, Thomas Lovett, Radia Perlman, Greg Regnier, Anil Vasudevan, Hugh Wilkinson
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Publication number: 20190386934Abstract: This disclosure describes enhancements to Ethernet for use in higher performance applications like Storage, HPC, and Ethernet based fabric interconnects. This disclosure provides various mechanisms for lossless fabric enhancements with error-detection and retransmissions to improve link reliability, frame pre-emption to allow higher priority traffic over lower priority traffic, virtual channel support for deadlock avoidance by enhancing Class of service functionality defined in IEEE 802.1Q, a new header format for efficient forwarding/routing in the fabric interconnect and header CRC for reliable cut-through forwarding in the fabric interconnect. The enhancements described herein, when added to standard and/or proprietary Ethernet protocols, broadens the applicability of Ethernet to newer usage models and fabric interconnects that are currently served by alternate fabric technologies like Infiniband, Fibre Channel and/or other proprietary technologies, etc.Type: ApplicationFiled: August 28, 2019Publication date: December 19, 2019Applicant: Intel CorporationInventors: Ilango Ganga, Alain Gravel, Thomas Lovett, Radia Perlman, Greg Regnier, Anil Vasudevan, Hugh Wilkinson
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Patent number: 10404625Abstract: This disclosure describes enhancements to Ethernet for use in higher performance applications like Storage, HPC, and Ethernet based fabric interconnects. This disclosure provides various mechanisms for lossless fabric enhancements with error-detection and retransmissions to improve link reliability, frame pre-emption to allow higher priority traffic over lower priority traffic, virtual channel support for deadlock avoidance by enhancing Class of service functionality defined in IEEE 802.1Q, a new header format for efficient forwarding/routing in the fabric interconnect and header CRC for reliable cut-through forwarding in the fabric interconnect. The enhancements described herein, when added to standard and/or proprietary Ethernet protocols, broadens the applicability of Ethernet to newer usage models and fabric interconnects that are currently served by alternate fabric technologies like Infiniband, Fiber Channel and/or other proprietary technologies, etc.Type: GrantFiled: September 25, 2014Date of Patent: September 3, 2019Assignee: Intel CorporationInventors: Ilango Ganga, Alain Gravel, Thomas Lovett, Radia Perlman, Greg Regnier, Anil Vasudevan, Hugh Wilkinson
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Patent number: 10205667Abstract: One embodiment provides a method for enabling class-based credit flow control for a network node in communication with a link partner using an Ethernet communications protocol. The method includes receiving a control frame from the link partner. The control frame includes at least one field for specifying credit for at least one traffic class and the credit is based on available space in a receive buffer associated with the at least one traffic class. The method further includes sending data packets to the link partner based on the credit, the data packets associated with the at least one traffic class.Type: GrantFiled: June 5, 2017Date of Patent: February 12, 2019Assignee: Intel CorporationInventors: Ilango Ganga, Alain Gravel, Thomas D. Lovett, Radia Perlman, Greg Regnier, Anil Vasudevan, Hugh Wilkinson
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Publication number: 20170272370Abstract: One embodiment provides a method for enabling class-based credit flow control for a network node in communication with a link partner using an Ethernet communications protocol. The method includes receiving a control frame from the link partner. The control frame includes at least one field for specifying credit for at least one traffic class and the credit is based on available space in a receive buffer associated with the at least one traffic class. The method further includes sending data packets to the link partner based on the credit, the data packets associated with the at least one traffic class.Type: ApplicationFiled: June 5, 2017Publication date: September 21, 2017Applicant: Intel CorporationInventors: ILANGO GANGA, ALAIN GRAVEL, THOMAS D. LOVETT, RADIA PERLMAN, GREG REGNIER, ANIL VASUDEVAN, HUGH WILKINSON
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Patent number: 9674098Abstract: One embodiment provides a method for enabling class-based credit flow control for a network node in communication with a link partner using an Ethernet communications protocol. The method includes receiving a control frame from the link partner. The control frame includes at least one field for specifying credit for at least one traffic class and the credit is based on available space in a receive buffer associated with the at least one traffic class. The method further includes sending data packets to the link partner based on the credit, the data packets associated with the at least one traffic class.Type: GrantFiled: June 24, 2014Date of Patent: June 6, 2017Assignee: INTEL CORPORATIONInventors: Ilango Ganga, Alain Gravel, Radia Perlman, Greg Regnier, Anil Vasudevan, Hugh Wilkinson, Thomas D. Lovett
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Publication number: 20150117177Abstract: This disclosure describes enhancements to Ethernet for use in higher performance applications like Storage, HPC, and Ethernet based fabric interconnects. This disclosure provides various mechanisms for lossless fabric enhancements with error-detection and retransmissions to improve link reliability, frame pre-emption to allow higher priority traffic over lower priority traffic, virtual channel support for deadlock avoidance by enhancing Class of service functionality defined in IEEE 802.1Q, a new header format for efficient forwarding/routing in the fabric interconnect and header CRC for reliable cut-through forwarding in the fabric interconnect. The enhancements described herein, when added to standard and/or proprietary Ethernet protocols, broadens the applicability of Ethernet to newer usage models and fabric interconnects that are currently served by alternate fabric technologies like Infiniband, Fibre Channel and/or other proprietary technologies, etc.Type: ApplicationFiled: September 25, 2014Publication date: April 30, 2015Inventors: Ilango Ganga, Alain Gravel, Thomas Lovett, Radia Perlman, Greg Regnier, Anil Vasudevan, Hugh Wilkinson
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Publication number: 20150009823Abstract: One embodiment provides a method for enabling class-based credit flow control for a network node in communication with a link partner using an Ethernet communications protocol. The method includes receiving a control frame from the link partner. The control frame includes at least one field for specifying credit for at least one traffic class and the credit is based on available space in a receive buffer associated with the at least one traffic class. The method further includes sending data packets to the link partner based on the credit, the data packets associated with the at least one traffic class.Type: ApplicationFiled: June 24, 2014Publication date: January 8, 2015Inventors: Ilango Ganga, Alain Gravel, Anil Vasudevan, Radia Perlman, Greg Regnier, Anil Vasudevan, Hugh Wilkinson
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Publication number: 20100257294Abstract: In some embodiments a system includes one or more processing nodes, a backplane, and one or more links to couple the one or more processing nodes to the backplane, wherein at least one of the one or more links is configurable as a standard Input/Output link and/or as a proprietary link. Other embodiments are described and claimed.Type: ApplicationFiled: April 6, 2009Publication date: October 7, 2010Inventors: Greg Regnier, Sorin Iacobovici, Chetan Hiremath, Udayan Mukherjee, Nilesh Jain
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Patent number: 7370137Abstract: Address translation for a source and destination of the data that utilizes different page tables. A direct memory access (DMA) engine is used as a memory-to-memory copy engine by utilizing a page-table walk and address translation for a source side of the copy, and an independent page-table walk and address translation for a destination side of the copy.Type: GrantFiled: June 6, 2005Date of Patent: May 6, 2008Assignee: Intel CorporationInventor: Greg Regnier
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Publication number: 20070162641Abstract: A direct memory access (“DMA”) request specifies a target address within an input/output virtual address (“IOVA”) space. The DMA target is validated and data are transferred between the target identified by the IOVA and a second location. Chipsets and systems using embodiments of the invention are also described and claimed.Type: ApplicationFiled: December 28, 2005Publication date: July 12, 2007Inventors: Ali Oztaskin, Rajesh Madukkarumukumana, Greg Regnier
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Publication number: 20060277357Abstract: An discussion of an address translation for a source and a destination of the data that utilizes different page tables. For example, a direct memory access (DMA) engine is used as a memory-to-memory copy engine by utilizing a page-table walk and address translation for a source side of the copy, and an independent page-table walk and address translation for a destination side of the copy.Type: ApplicationFiled: June 6, 2005Publication date: December 7, 2006Inventor: Greg Regnier
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Publication number: 20060123130Abstract: Proxy nodes perform TCP/IP processing on behalf of application nodes, utilize lightweight protocols to communicate with application nodes, and communicate with network nodes and network clients using Transmission Control Protocol/Internet Protocol (TCP/IP).Type: ApplicationFiled: January 24, 2006Publication date: June 8, 2006Inventors: Hemal Shah, Greg Regnier, Annie Foong
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Publication number: 20060072563Abstract: In general, the disclosure describes a variety of techniques that can enhance packet processing operations.Type: ApplicationFiled: October 5, 2004Publication date: April 6, 2006Inventors: Greg Regnier, Vikram Saletore, Gary McAlpine, Ram Huggahalli, Ravishankar Iyer, Ramesh Illikkal, David Minturn, Donald Newell, Srihari Makineni
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Publication number: 20050144422Abstract: A virtual to physical address translator in which a requesting process supplements a virtual memory address with a shortcut to a physical address associated with one level of a multi-level virtual address translation table. A second process, such as an I/O process, receives the shortcut and the virtual address and uses an address translator to determine the physical address. In some implementations, the shortcut may be made opaque to the requesting process such that the requesting process cannot determine the physical address represented in the shortcut.Type: ApplicationFiled: December 30, 2003Publication date: June 30, 2005Inventors: Gary McAlpine, Dave Minturn, Greg Regnier, Frank Berry
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Publication number: 20050058147Abstract: A data network and a method for providing prioritized data movement between endpoints connected by multiple logical channels. Such a data network may include a first node comprising a first plurality of first-in, first-out (FIFO) queues arranged for high priority to low priority data movement operations; and a second node operatively connected to the first node by multiple control and data channels, and comprising a second plurality of FIFO queues arranged in correspondence with the first plurality of FIFO queues for high priority to low priority data movement operations via the multiple control and data channels; wherein an I/O transaction is accomplished by one or more control channels and data channels created between the first node and the second node for moving commands and data for the I/O transaction during the data movement operations, in the order from high priority to low priority.Type: ApplicationFiled: October 27, 2004Publication date: March 17, 2005Inventors: Greg Regnier, Jeffrey Butler, Dave Minturn