Patents by Inventor Gregg Baeckler
Gregg Baeckler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230222275Abstract: A method is provided for processing code for a circuit design for an integrated circuit using a computer system. The method includes receiving at least a portion of the code for the circuit design for the integrated circuit, wherein the portion of the code comprises an error or has incomplete constraints, making an assumption about the error and the missing constraints using a computer aid design tool, and generating a revised circuit design for the integrated circuit with the error corrected and any missing constraints added based on the assumption and based on the code using the computer aided design tool and a library of components for circuit designs.Type: ApplicationFiled: March 16, 2023Publication date: July 13, 2023Applicant: Intel CorporationInventors: Gregg Baeckler, Mahesh A. Iyer, Martin Langhammer
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Publication number: 20230116554Abstract: A processor circuit includes a compiler configured to receive a software program that comprises software code coded in an assembly language and inline software code coded in a high-level programming language, compile the inline software code coded in the high-level programming language within the software program into assembly code in the assembly language, and compile the assembly code and the software code coded in the assembly language into machine code for the processor circuit. A method includes determining if first and second instructions in a software program are combinable into one instruction word, combining the first and the second instructions in the software program into one instruction word if the first and the second instructions are combinable, and fetching the instruction word into a single register by storing the instruction word in the single register.Type: ApplicationFiled: December 7, 2022Publication date: April 13, 2023Applicant: Intel CorporationInventors: Gregg Baeckler, Martin Langhammer
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Patent number: 11010134Abstract: Systems, methods, and devices for enhancing performance/efficiency of soft multiplier implementations are provided. More specifically, a method to implement soft multipliers with a high radix subset code architecture is provided. The techniques provided herein result in smaller multipliers that consume less area, improve packing, consume less power, and improve routing options on an integrated circuit.Type: GrantFiled: September 28, 2017Date of Patent: May 18, 2021Assignee: Intel CorporationInventors: Martin Langhammer, Gregg Baeckler
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Patent number: 10715144Abstract: Integrated circuits with programmable logic regions are provided. The programmable logic regions may be organized into smaller logic units sometimes referred to as a logic cell. A logic cell may include four 4-input lookup tables (LUTs) coupled to an adder carry chain. Each of the four 4-input LUTs may include two 3-input LUTs and a selector multiplexer. The carry chain may include at three or more full adder circuits. The outputs of the 3-input LUTs may be directly connected to inputs of the full adder circuits in the carry chain. By providing at least the same or more number of full adder circuits as the total number of 4-input LUTs in the logic cell, the arithmetic density of the logic is enhanced.Type: GrantFiled: June 6, 2019Date of Patent: July 14, 2020Assignee: Intel CorporationInventors: Sergey Gribok, Gregg Baeckler, Martin Langhammer
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Publication number: 20190288688Abstract: Integrated circuits with programmable logic regions are provided. The programmable logic regions may be organized into smaller logic units sometimes referred to as a logic cell. A logic cell may include four 4-input lookup tables (LUTs) coupled to an adder carry chain. Each of the four 4-input LUTs may include two 3-input LUTs and a selector multiplexer. The carry chain may include at three or more full adder circuits. The outputs of the 3-input LUTs may be directly connected to inputs of the full adder circuits in the carry chain. By providing at least the same or more number of full adder circuits as the total number of 4-input LUTs in the logic cell, the arithmetic density of the logic is enhanced.Type: ApplicationFiled: June 6, 2019Publication date: September 19, 2019Applicant: Intel CorporationInventors: Sergey Gribok, Gregg Baeckler, Martin Langhammer
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Patent number: 10177766Abstract: Logic elements (LE) that can provide a number of features. For example, the LE can provide efficient and flexible use of look up tables (LUTs) and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality to provide various modes of operation that enable the various features of the LE.Type: GrantFiled: November 14, 2016Date of Patent: January 8, 2019Assignee: Altera CorporationInventors: James Schleicher, Richard Yuan, Bruce Pedersen, Sinan Kaptanoglu, Gregg Baeckler, David Lewis, Mike Hutton, Andy L. Lee, Rahul Saini, Henry Kim
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Publication number: 20180364981Abstract: Systems, methods, and devices for enhancing performance/efficiency of soft multiplier implementations are provided. More specifically, a method to implement soft multipliers with a high radix subset code architecture is provided. The techniques provided herein result in smaller multipliers that consume less area, improve packing, consume less power, and improve routing options on an integrated circuit.Type: ApplicationFiled: September 28, 2017Publication date: December 20, 2018Inventors: Martin Langhammer, Gregg Baeckler
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Patent number: 9496875Abstract: Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.Type: GrantFiled: September 30, 2014Date of Patent: November 15, 2016Assignee: Altera CorporationInventors: James Schleicher, Richard Yuan, Bruce Pedersen, Sinan Kaptanoglu, Gregg Baeckler, David Lewis, Mike Hutton, Andy L. Lee, Rahul Saini, Henry Kim
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Patent number: 8878567Abstract: Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.Type: GrantFiled: October 24, 2013Date of Patent: November 4, 2014Assignee: Altera CorporationInventors: James Schleicher, Richard Yuan, Bruce Pedersen, Sinan Kaptanoglu, Gregg Baeckler, David Lewis, Mike Hutton, Andy L. Lee, Rahul Saini, Henry Kim
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Patent number: 8593174Abstract: Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.Type: GrantFiled: June 29, 2012Date of Patent: November 26, 2013Assignee: Altera CorporationInventors: James Schleicher, Richard Yuan, Bruce Pedersen, Sinan Kaptanoglu, Gregg Baeckler, David Lewis, Mike Hutton, Andy Lee, Rahul Saini, Henry Kim
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Patent number: 8402408Abstract: An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.Type: GrantFiled: December 28, 2011Date of Patent: March 19, 2013Assignee: Altera CorporationInventors: Babette van Antwerpen, Michael D. Hutton, Gregg Baeckler, Richard Yuan
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Patent number: 8237465Abstract: Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.Type: GrantFiled: March 17, 2011Date of Patent: August 7, 2012Assignee: Altera CorporationInventors: James Schleicher, Richard Yuan, Bruce Pedersen, Sinan Kaptanoglu, Gregg Baeckler, David Lewis, Mike Hutton, Andy Lee, Rahul Saini, Henry Kim
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Patent number: 8108812Abstract: An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.Type: GrantFiled: March 30, 2010Date of Patent: January 31, 2012Assignee: Altera CorporationInventors: Babette van Antwerpen, Michael D. Hutton, Gregg Baeckler, Richard Yuan
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Patent number: 7911230Abstract: Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.Type: GrantFiled: April 16, 2009Date of Patent: March 22, 2011Assignee: Altera CorporationInventors: James Schleicher, Richard Yuan, Bruce Pedersen, Sinan Kaptanoglu, Gregg Baeckler, David Lewis, Mike Hutton, Andy Lee, Rahul Saini, Henry Kim
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Patent number: 7689955Abstract: An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.Type: GrantFiled: August 30, 2006Date of Patent: March 30, 2010Assignee: Altera CorporationInventors: Babette van Antwerpen, Michael D. Hutton, Gregg Baeckler, Richard Yuan
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Patent number: 7671625Abstract: Disclosed is an LE that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.Type: GrantFiled: March 5, 2008Date of Patent: March 2, 2010Assignee: Altera CorporationInventors: James Schleicher, Richard Yuan, Bruce Pedersen, Sinan Kaptanoglu, Gregg Baeckler, David Lewis, Michael Hutton, Andy Lee, Rahul Saini, Henry Kim
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Patent number: 7636655Abstract: Programmable devices include configurable logic hardware for implementing logic gates, registers for storing data, and secondary hardware for additional functions, such as loading and clearing. The secondary hardware can implement portions of the user design, thereby decreasing the number of gates to be implemented elsewhere. A set of possible alternative implementations of portions of the user design is identified by enumerating the inputs connected with a register. Logic diagrams are created for the set of inputs, and alternative implementations are identified from the logic diagrams by recognizing patterns similar to the secondary hardware functions. To determine an implementation that balances gate savings against routing costs, alternative implementations are grouped according to compatible inputs and ranked by the number of registers in each group. The implementation with the highest rank is selected, and selected registers are removed from other alternative implementations.Type: GrantFiled: December 8, 2003Date of Patent: December 22, 2009Assignee: Altera CorporationInventor: Gregg Baeckler
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Patent number: 7594208Abstract: Techniques for optimizing the placement and synthesis of a circuit design on a programmable integrated circuit are provided. The performance of a circuit design is analyzed after it has been compiled with different values for selected input parameters. The input parameter values that produce the best results for an output metric are then chosen to synthesis and place the circuit design on the programmable integrated circuit. In one embodiment, the values of the output metrics are averaged for all test compiles that share the same input parameters, but different seeds. In another embodiment, the compile with the best output metrics, as determined by the user, are selected. These techniques allow a user to automatically trade off compile-time to get a better-optimized circuit.Type: GrantFiled: December 13, 2006Date of Patent: September 22, 2009Assignee: Altera CorporationInventors: Terry Borer, Ian Chesal, James Schleicher, David Mendel, Mike Hutton, Boris Ratchev, Yaska Sankar, Babette van Antwerpen, Gregg Baeckler, Richard Yuan, Stephen Brown, Vaughn Betz, Kevin Chan
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Patent number: 7565388Abstract: Logic circuits that support the addition of three binary numbers using hardwired adders are described. In one embodiment, this is accomplished by using a 3:2 compressor (i.e., a Carry Save Adder method), using hardwired adders to add the sums and carrys produced by the 3:2 compression, and sharing carrys data calculated in one logic element (“LE”) with the following LE. In such an embodiment, with the exception of the first and last LEs in a logic array block (“LAB”), each LE in effect lends one look-up table (“LUT”) to the LE below (i.e., the following LE) and borrows one LUT from the LE above (i.e., the previous LE). The LUT being lent or borrowed is one that implements the carry function in the 3:2 compressor model. In another aspect, an embodiment of the present invention provides LEs that include selectors to select signals corresponding to the addition of three binary numbers mode.Type: GrantFiled: November 21, 2003Date of Patent: July 21, 2009Assignee: Altera CorporationInventors: Gregg Baeckler, Martin Langhammer, James Schleicher, Richard Yuan
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Patent number: 7538579Abstract: Disclosed is an LE that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.Type: GrantFiled: December 1, 2006Date of Patent: May 26, 2009Assignee: Altera CorporationInventors: James Schleicher, Richard Yuan, Bruce Pedersen, Sinan Kaptanoglu, Gregg Baeckler, David Lewis, Mike Hutton, Andy Lee, Rahul Saini, Henry Kim