Patents by Inventor Gregg Bouchard
Gregg Bouchard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9531723Abstract: A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. Each of the lookup engines receives a key request associated with a packet and determines a subset of the rules to match against the packet data. Based on a prefetch status, a selection of the subset of rules are retrieved for rule matching. As a result of the rule matching, the lookup engine returns a response message indicating whether a match is found.Type: GrantFiled: December 29, 2014Date of Patent: December 27, 2016Assignee: Cavium, Inc.Inventors: Gregg A. Bouchard, Rajan Goyal
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Patent number: 9531647Abstract: A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. A lookup front-end receives lookup requests from multiple hosts, manages traffic among the hosts, and processes these lookup requests to generate key requests for forwarding to the lookup engines. As a result of the rule matching, the lookup engine returns a response message indicating whether a match is found. The lookup front-end further processes the response message and provides a corresponding response to the host.Type: GrantFiled: March 15, 2013Date of Patent: December 27, 2016Assignee: Cavium, Inc.Inventors: Rajan Goyal, Gregg A. Bouchard, Troy S. Dahlmann, Jeffrey Richard Hardesty, Karen A. Szypulski
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Patent number: 9525630Abstract: A method, and corresponding apparatus, of assigning processing resources used to manage transport operations between a first memory cluster and one or more other memory clusters, include receiving information indicative of allocation of a subset of processing resources in each of the one or more other memory clusters to the first memory cluster, storing, in the first memory cluster, the information indicative of resources allocated to the first memory cluster, and facilitating management of transport operations between the first memory cluster and the one or more other memory clusters based at least in part on the information indicative of resources allocated to the first memory cluster.Type: GrantFiled: August 2, 2012Date of Patent: December 20, 2016Assignee: Cavium, Inc.Inventors: Najeeb I. Ansari, Gregg A. Bouchard, Rajan Goyal, Jeffrey A. Pangborn
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Patent number: 9497117Abstract: A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. A lookup front-end receives lookup requests from a host, and processes these lookup requests to generate key requests for forwarding to the lookup engines. As a result of the rule matching, the lookup engine returns a response message indicating whether a match is found. The lookup front-end further processes the response message and provides a corresponding response to the host.Type: GrantFiled: November 18, 2013Date of Patent: November 15, 2016Assignee: Cavium, Inc.Inventors: Rajan Goyal, Gregg A. Bouchard, Jeffrey R. Hardesty, Troy S. Dahlmann, Karen A. Szypulski
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Publication number: 20160248739Abstract: In one embodiment, a system includes a format block configured to receive a key, at least one rule, and rule formatting information. The rule can have one or more dimensions. The format block can be further configured to extract each of the dimensions from the at least one rule. The system can further include a plurality of dimension matching engines (DME). Each DME can be configured to receive the key and a corresponding formatted dimension, and process the key and the corresponding dimension for returning a match or nomatch. The system can further include a post processing block configured to analyze the matches or no matches returned from the DMEs and return a response based on the returned matches or nomatches.Type: ApplicationFiled: May 3, 2016Publication date: August 25, 2016Inventors: Gregg A. Bouchard, Rajan Goyal, Gregory E. Lund
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Publication number: 20160232210Abstract: An improved content search mechanism uses a graph that includes intelligent nodes avoids the overhead of post processing and improves the overall performance of a content processing application. An intelligent node is similar to a node in a DFA graph but includes a command. The command in the intelligent node allows additional state for the node to be generated and checked. This additional state allows the content search mechanism to traverse the same node with two different interpretations. By generating state for the node, the graph of nodes does not become exponential. It also allows a user function to be called upon reaching a node, which can perform any desired user tasks, including modifying the input data or position.Type: ApplicationFiled: April 21, 2016Publication date: August 11, 2016Inventors: Muhammad R. Hussain, David A. Carlson, Gregg A. Bouchard, Trent Parker
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Patent number: 9391892Abstract: A method and corresponding apparatus of managing transport operations between a first memory cluster and one or more other memory clusters, include receiving, in the first cluster, information related to one or more transport operations with related data buffered in an interface device, the interface device coupling the first cluster to the one or more other clusters, selecting at least one transport operation, from the one or more transport operations, based at least in part on the received information, and executing the selected at least one transport operation.Type: GrantFiled: August 2, 2012Date of Patent: July 12, 2016Assignee: Cavium, Inc.Inventors: Najeeb I. Ansari, Gregg A. Bouchard, Rajan Goyal, Jeffrey A. Pangborn
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Patent number: 9344366Abstract: In one embodiment, a system includes a format block configured to receive a key, at least one rule, and rule formatting information. The rule can have one or more dimensions. The format block can be further configured to extract each of the dimensions from the at least one rule. The system can further include a plurality of dimension matching engines (DME). Each DME can be configured to receive the key and a corresponding formatted dimension, and process the key and the corresponding dimension for returning a match or nomatch. The system can further include a post processing block configured to analyze the matches or no matches returned from the DMEs and return a response based on the returned matches or nomatches.Type: GrantFiled: August 2, 2012Date of Patent: May 17, 2016Assignee: Cavium, Inc.Inventors: Gregg A. Bouchard, Rajan Goyal, Gregory E. Lund
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Patent number: 9336328Abstract: An improved content search mechanism uses a graph that includes intelligent nodes avoids the overhead of post processing and improves the overall performance of a content processing application. An intelligent node is similar to a node in a DFA graph but includes a command. The command in the intelligent node allows additional state for the node to be generated and checked. This additional state allows the content search mechanism to traverse the same node with two different interpretations. By generating state for the node, the graph of nodes does not become exponential. It also allows a user function to be called upon reaching a node, which can perform any desired user tasks, including modifying the input data or position.Type: GrantFiled: July 22, 2014Date of Patent: May 10, 2016Assignee: Cavium, Inc.Inventors: Muhammad R. Hussain, David A. Carlson, Gregg A. Bouchard, Trent Parker
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Patent number: 9319316Abstract: A method and corresponding apparatus of managing transport operations between a first memory cluster and one or more other memory clusters, include selecting, at a clock cycle in the first memory cluster, at least one transport operation destined to at least one destination memory cluster, from one or more transport operations, based at least in part on priority information associated with the one or more transport operations or current states of available processing resources allocated to the first memory cluster in each of a subset of the one or more other memory clusters, and initiating the transport of the selected at least one transport operation.Type: GrantFiled: August 2, 2012Date of Patent: April 19, 2016Assignee: Cavium, Inc.Inventors: Najeeb I. Ansari, Gregg A. Bouchard, Rajan Goyal, Jeffrey A. Pangborn
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Patent number: 9276846Abstract: A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. A lookup front-end receives lookup requests from a host, and processes these lookup requests to generate key requests for forwarding to the lookup engines. Based on information in the packet, the lookup front-end can optimize start times for sending key requests as a continuous stream with minimal delay. As a result of the rule matching, the lookup engine returns a response message indicating whether a match is found.Type: GrantFiled: March 15, 2013Date of Patent: March 1, 2016Assignee: Cavium, Inc.Inventors: Rajan Goyal, Gregg A. Bouchard, Karen A. Szypulski, Charles D. Spackman
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Patent number: 9225643Abstract: A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. Each of the lookup engines receives a key request associated with a packet and determines a subset of the rules to match against the packet data. As a result of the rule matching, the lookup engine returns a response message indicating whether a match is found.Type: GrantFiled: March 17, 2015Date of Patent: December 29, 2015Assignee: Cavium, Inc.Inventors: Rajan Goyal, Gregg A. Bouchard
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Publication number: 20150288700Abstract: A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. Each of the lookup engines receives a key request associated with a packet and determines a subset of the rules to match against the packet data. Based on a prefetch status, a selection of the subset of rules are retrieved for rule matching. As a result of the rule matching, the lookup engine returns a response message indicating whether a match is found.Type: ApplicationFiled: December 29, 2014Publication date: October 8, 2015Inventors: Gregg A. Bouchard, Rajan Goyal
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Patent number: 9141548Abstract: A network services processor includes an input/output bridge that avoids unnecessary updates to memory when cache blocks storing processed packet data are no longer required. The input/output bridge monitors requests to free buffers in memory received from cores and IO units in the network services processor. Instead of writing the cache block back to the buffer in memory that will be freed, the input/output bridge issues don't write back commands to a cache controller to clear the dirty bit for the selected cache block, thus avoiding wasteful write-backs from cache to memory. After the dirty bit is cleared, the buffer in memory is freed, that is, made available for allocation to store data for another packet.Type: GrantFiled: January 20, 2014Date of Patent: September 22, 2015Assignee: Cavium, Inc.Inventors: David H. Asher, Gregg A. Bouchard, Richard E. Kessler, Robert A. Sanzone
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Patent number: 9130819Abstract: In a network search processor, configured to handle search requests in a router, a scheduler for scheduling rule matching threads initiated by a plurality of initiating engines is designed to make efficient use of the resources in the network search processor while providing high speed performance. According to at least one example embodiment, the scheduler and a corresponding scheduling method comprise: determining a set of bundles of rule matching threads, each bundle being initiated by a separate initiating engine; distributing rule matching threads in each bundle into a number of subgroups of rule matching threads; assigning the subgroups of rule matching threads associated with each bundle of the set of bundles to multiple scheduling queues; and sending rule matching threads, assigned to each scheduling queue, to rule matching engines according to an order based on priorities associated with the respective bundles of rule matching threads.Type: GrantFiled: March 15, 2013Date of Patent: September 8, 2015Assignee: Cavium, Inc.Inventors: Jeffrey A. Pangborn, Najeeb I. Ansari, Gregg A. Bouchard, Rajan Goyal
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Patent number: 9112767Abstract: According to at least one example embodiment, a method and a corresponding accumulator scoreboard for managing bundles of rule matching threads processed by one or more rule matching engines comprise: recording, for each rule matching thread in a given bundle of rule matching threads, a rule matching result in association with a priority corresponding to the respective rule matching thread; determining a final rule matching result, for the given bundle of rule matching threads, based at least in part on the corresponding indications of priorities; and generating a response state indicative of the determined final rule matching result for reporting to a host processor or a requesting processing engine.Type: GrantFiled: March 15, 2013Date of Patent: August 18, 2015Assignee: Cavium, Inc.Inventors: Najeeb I. Ansari, Gregg A. Bouchard, Rajan Goyal, Jeffrey A. Pangborn
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Publication number: 20150195200Abstract: A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. Each of the lookup engines receives a key request associated with a packet and determines a subset of the rules to match against the packet data. As a result of the rule matching, the lookup engine returns a response message indicating whether a match is found.Type: ApplicationFiled: March 17, 2015Publication date: July 9, 2015Inventors: Rajan Goyal, Gregg A. Bouchard
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Patent number: 9065860Abstract: A processor with on-chip memory including a plurality of physical memory banks is disclosed. The processor includes a method, and corresponding apparatus, of enabling multi-access to the plurality of physical memory banks. The method comprises selecting a subset of multiple access requests to be executed in at least one clock cycle over at least one of a number of access ports connected to the plurality of physical memory banks, the selected subset of access requests addressed to different physical memory banks, among the plurality of memory banks, and scheduling the selected subset of access requests, each over a separate access port.Type: GrantFiled: August 2, 2012Date of Patent: June 23, 2015Assignee: Cavium, Inc.Inventors: Jeffrey A. Pangborn, Gregg A. Bouchard, Rajan Goyal, Najeeb I. Ansari, Ahmed Shahid
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Publication number: 20150143060Abstract: According to an example embodiment, a processor is provided including an integrated on-chip memory device component. The on-chip memory device component includes a plurality of memory banks, and multiple logical ports, each logical port coupled to one or more of the plurality of memory banks, enabling access to multiple memory banks, among the plurality of memory banks, per clock cycle, each memory bank accessible by a single logical port per clock cycle and each logical port accessing a single memory bank per clock cycle.Type: ApplicationFiled: January 26, 2015Publication date: May 21, 2015Inventors: Gregg A. Bouchard, Rajan Goyal, Jeffrey A. Pangborn, Najeeb I. Ansari
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Patent number: 9031075Abstract: A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. A lookup front-end receives lookup requests from a host, and processes these lookup requests to generate key requests for forwarding to the lookup engines. As a result of the rule matching, the lookup engine returns a response message indicating whether a match is found. The lookup front-end further processes the response message and provides a corresponding response to the host.Type: GrantFiled: December 23, 2013Date of Patent: May 12, 2015Assignee: Cavium, Inc.Inventors: Rajan Goyal, Gregg A. Bouchard