Abstract: A programmable linear transconductor circuit is disclosed. The programmable linear transconductor circuit includes a first current source and a second current source, a first group of transistors and a second group of transistors, a first load coupled to the first group of transistors, and a second load coupled to the second group of transistors, and a first group of switches and a second group of switches. Each switch in the first group of switches is selectively connected to a transistor from the first group of transistors to the first current source or the second current source. Similarly, each switch in the second group of switches is selectively connected to a transistor from the second group of transistors to the first current source or the second current source, accordingly.

Abstract: An active voltage divide circuit is disclosed. The voltage divider circuit includes a pair of complementary inputs separated by a common input signal node, a pair of complementary outputs, and a pair of divider circuits coupled between the pair of complementary inputs and the pair of complementary outputs. The pair of divider circuits divide input voltages at the pair of complementary inputs, and produces the divided input voltages appear at the pair of complementary outputs, respectively.

Abstract: A DC offset cancellation circuit receives two input signals. A first one of the input signals is amplified by an amplifier, and the amplified output signal of the amplifier is tracked and held during a first clock phase. Simultaneously, during the first clock phase, the second one of the input signals is tracked and held. During the second clock phase succeeding the first clock phase, the stored second one of the input signals is amplified by the same amplifier that was used to amplify the first one of the input signals. The amplified and stored first one of the input signals and the amplified second one of the input signals are summed during the second clock phase to remove any DC offset. The summed signals are sampled and held during the second clock phase. The offset of the summer circuit can be canceled by sequential digital processing.

Abstract: An MR head circuit including a differential amplifier, means for applying a dc bias to the head, a capacitor mounted in parallel to the head to eliminate the dc voltage offset, and a feedback loop configured for evaluating the differential voltage and for controlling the current in portions of the amplifier to rapidly charge the capacitor upon circuit activation. The feedback loop also includes a thermal asperity compensator configured for producing a given signal, both upon activation of the circuit and when the magnitude of the voltage differential exceeds a given value, and the feedback loop includes means responsive to the given signal for altering select current paths of the feedback loop to thereby produce elevated charging currents in the differential amplifier during initial activation, and to increase the ac gain of the feedback loop at other times so as to raise the lower corner frequency of the differential amplifier to filter out the relatively low frequency of a thermal asperity waveform.

Abstract: An apparatus for providing a varying impedance point in a circuit corresponding to a frequency of an input signal applied to the apparatus. Device sizes of the apparatus can be selected to provide varying impedance for desired frequency ranges.

Abstract: An improved current mirror circuit with isolation of the output leg for improved stabilization of the circuit even when heavily loaded.

Abstract: A circuit for converting received input signals to highly symmetrical CMOS level outputs having fast slew rates. The circuit can accept a differential input signal with a wide range of common mode voltages. A first stage level shifts the input signals to provide a ground-based common mode output to a second stage level shifter which centers the input signals around the midpoint between V.sub.cc and ground and which increases their voltage swing. The final stage provides a full, highly symmetric, rail-to-rail output capable of driving highly capacitive loads at high rates and which is immune to temperature, V.sub.cc, and process variations.

Abstract: A high speed bi-polar D latch circuit uses cross-coupled current-biased buffering transistors to block control current from output resistors so that the clock and data controls are not connected directly to the outputs of the latch. The memory cell portion of the latch which controls the latch output is constantly biased. Latch output swing is minimally affected by clock/data switching due to the buffering action of the emitter followers on the latch outputs. Changing the latch state is accomplished by changing the base-emitter voltage of the buffering transistors through the emitter followers. The circuit provides greater noise immunity at latch outputs during clock transitions and faster rise/fall times of output waveforms.

Abstract: A signal detector circuit in a data receiver including a programmable hysteresis circuit for setting and detecting the presence of both a threshold minimum data signal level and a reset signal level higher than the minimum signal level.