Abstract: A method, computer program product, and/or system is disclosed for identifying special cases for testing an integrated circuit that includes defining interesting cases, preferably by a user; obtaining an instruction from an instruction set architecture (ISA); determining that there is an interesting case for the obtained instruction; computing (i) a size of the input space (I0) of the ISA, and (ii) an interesting case space (Ii) which is an input space leading to the interesting case for the obtained instruction; obtaining a special case fraction by dividing the interesting case space (Ii) by the input space (I0); determining a special case fraction (Ii)/(I0) is less than a threshold; and identifying, in response to the special case fraction being less than the threshold, the interesting case as a special case. In an approach the special case is documented.

Abstract: A test stimulus generator generates error irritations, or error sequences, within a processor system. The test stimulus generator includes an initialization register, a pseudo-random number generator (PRNG), a clock subsystem, and an output register. The PRNG calculates an output value from an initialization value stored in the initialization register. The PRNG output value represents a unique error irritation and identifies one or more components within the processor system to handle the error irritation. The clock subsystem generates either a continuous or pulsed clock signal that transfers the initialization value into the PRNG. The output register stores the PRNG output value and transmits the corresponding error irritation to the processor components identified to handle the error irritation. The test stimulus generator generates error irritations in a predetermined or random order based on the initialization value. A corresponding method and computer program product are also disclosed.

Abstract: A method, computer program product, and/or system is disclosed for identifying special cases for testing an integrated circuit that includes defining interesting cases, preferably by a user; obtaining an instruction from an instruction set architecture (ISA); determining that there is an interesting case for the obtained instruction; computing (i) a size of the input space (I0) of the ISA, and (ii) an interesting case space (Ii) which is an input space leading to the interesting case for the obtained instruction; obtaining a special case fraction by dividing the interesting case space (Ii) by the input space (I0); determining a special case fraction (Ii)/(I0) is less than a threshold; and identifying, in response to the special case fraction being less than the threshold, the interesting case as a special case. In an approach the special case is documented.

Abstract: A test stimulus generator generates error irritations, or error sequences, within a processor system. The test stimulus generator includes an initialization register, a pseudorandom number generator (PRNG), a clock subsystem, and an output register. The PRNG calculates an output value from an initialization value stored in the initialization register. The PRNG output value represents a unique error irritation and identifies one or more components within the processor system to handle the error irritation. The clock subsystem generates either a continuous or pulsed clock signal that transfers the initialization value into the PRNG. The output register stores the PRNG output value and transmits the corresponding error irritation to the processor components identified to handle the error irritation. The test stimulus generator generates error irritations in a predetermined or random order based on the initialization value. A corresponding method and computer program product are also disclosed.

Abstract: A method of performing instruction marking in a computer processor architecture includes fetching instructions from a memory unit by a fetching unit in the computer processor architecture. Instruction groups for marking are determined. Fetched instructions are matched to instruction groups for marking. The fetched instructions are marked. Some of the marked instructions are selectively unmarked. The marked and unmarked instructions are forwarded to a queue of instructions for processing in the computer processor architecture.